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Re: [avr-gcc-list] Accessing C sram locations in inline asm
From: |
Theodore A. Roth |
Subject: |
Re: [avr-gcc-list] Accessing C sram locations in inline asm |
Date: |
Fri, 6 Sep 2002 14:44:19 -0700 (PDT) |
Ah, my mistake. The LDS insn is a 32-bit one that needs an indirect
address as an operand. I think the documentation might be wrong about the
label.
I tried this test program:
#include <inttypes.h>
#include <avr/io.h>
uint8_t foo = 10;
uint8_t bar = 10;
int main (void)
{
asm volatile ("lds __tmp_reg__, foo" :: );
asm volatile ("lds __tmp_reg__, bar" :: );
return (0);
}
And got the following output:
>From my map file (generated with -Wl,-Map,messy.map):
.data 0x00800060 0x2 load address 0x000000ba
0x00800060 PROVIDE (__data_start, .)
*(.data)
.data 0x00800060 0x1 messy.o
0x00800060 foo
0x00800061 bar
>From my list file (generated with avr-objdump -S -D):
000000a4 <main>:
uint8_t foo = 10;
uint8_t bar = 10;
int main (void)
{
a4: cf ef ldi r28, 0xFF ; 255
a6: df e0 ldi r29, 0x0F ; 15
a8: de bf out 0x3e, r29 ; 62
aa: cd bf out 0x3d, r28 ; 61
asm volatile ("lds __tmp_reg__, foo" :: );
ac: 00 90 60 00 lds r0, 0x0060
asm volatile ("lds __tmp_reg__, bar" :: );
b0: 00 90 61 00 lds r0, 0x0061
return (0);
}
b4: 80 e0 ldi r24, 0x00 ; 0
b6: 90 e0 ldi r25, 0x00 ; 0
b8: 0c 94 5c 00 jmp 0xbc
This seems to work fine for me. foo is a global variable at 0x0060 and the
asm statement does what you want.
I wonder if you are having scoping problems?
Ted Roth
On Fri, 6 Sep 2002, Grant Stockly wrote:
:) At 01:21 PM 9/6/2002 -0700, you wrote:
:)
:)
:) >On Fri, 6 Sep 2002, Grant Stockly wrote:
:) >
:) >:) I tried. asm volatile("lds r24, %1" :: "label" (sram_byte) ); failed no
:) >:) matter what I tried. (Subtracting the memory start offset, etc.
:) >
:) >How about this:
:) >
:) > asm volatile("lds r24, %0" :: "r" (sram_byte) );
:) >
:) >sram_byte should end up in a register. Perform a disassemble with
:) >`avr-objdump -D -S' and examine the generated asm. It's usually very
:) >educational as to what the compiler is doing.
:)
:) I'd like to use the C sram locations hard coded. I have a ~400 asm
:) instruction cycle interrupt routine that needs to run 10,000 times a second
:) and have access to about 30 bytes of storage space. The routine has to be
:) optimized to run quickly, and run the exact (-+4 instruction cycles) no
:) matter what the result of about 16 conditional branches. It would be nice
:) and clean to be able to access SRAM by what the .bss segments say.
:)
:) asm volatile("lds r24, doesnt_exist" :: ); caused the linker to report
:) an error, so I assume that it will work. I'm going to code up a test
:) program and see what happens.
:)
:) I'll keep you posted.
:)
:) Grant
:)
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