Re: [avr-gcc-list] Mega 128 not optimising correctly ...

[E. Weddington]

Rob,

I answered this in AVRFreaks. My answer is reproduced below. Sorry 
for the screwed up indentation (cut + paste) :-).

Eric


Your solution:

                        Change the defines to:

                        /* ADC control and data line definitions 
(excluding the (possible many) SDIs) */
                        #define CS_LOW PORTD &= ~0x80 // CS low
                        #define CS_HIGH PORTD |= 0x80 // CS high

                        #define SDO_LOW PORTD &= ~0x20 // SDO low
                        #define SDO_HIGH PORTD |= 0x20 // SDO high

                        #define SCLK_LOW PORTD &= ~0x40; // SCLK low
                        #define SCLK_HIGH PORTD |= 0x40; // SCLK high

                        This is the more standard way of setting and 
clearing bits. It also happens to go through gcc better and
                        gets compiled to the code that you want.

                        Eric


On 30 Oct 2002 at 10:17, Rob Ward wrote:

> Hi. Firstly, thanks to the guys who replied to my first queries on
> this list about 6 months ago (Jeremy, Peter, Robert, Marek, Andreas).
> 
> Another question : I have the following code which compiles fine, but
> which gives what I think are inconsistent results...
> 
> First the #defines...
> 
> /* ADC control and data line definitions (excluding the (possible
> many) SDIs) */ #define CS_LOW (PORTD &= 0x7f) // CS low #define
> CS_HIGH (PORTD |= 0x80) // CS high #define SDO_LOW (PORTD &= 0xdf) //
> SDO low #define SDO_HIGH (PORTD |= 0x20) // SDO high #define SCLK_LOW
> (PORTD &= 0xbf) // SCLK low #define SCLK_HIGH (PORTD |= 0x40) // SCLK
> high
> 
> ...and now code...
> 
> void InitialiseADCs(void) {
>  u08 j;
> 
>  CS_LOW; // enable all ADCs
> 200: 97 98  cbi 0x12, 7 ; 18
> 
>  SDO_HIGH; // and send 127 ones, then 
> one zero.
> 202: 95 9a  sbi 0x12, 5 ; 18
> 
>  for (j=0; j<127; j++) {
> 204: 90 e0  ldi r25, 0x00 ; 0
> 
>  SCLK_HIGH;
> 206: 96 9a  sbi 0x12, 6 ; 18
> 
>  SCLK_LOW;
> 208: 2f eb  ldi r18, 0xBF ; 191
> 20a: 82 b3  in r24, 0x12 ; 18
> 20c: 82 23  and r24, r18
> 20e: 82 bb  out 0x12, r24 ; 18
> 
> 210: 9f 5f  subi r25, 0xFF ; 255
> 212: 9f 37  cpi r25, 0x7F ; 127
> 214: c0 f3  brcs .-16  ; 0x206
>  }
>  SDO_LOW;
> 216: 95 98  cbi 0x12, 5 ; 18
> 
>  SCLK_HIGH;
> 218: 96 9a  sbi 0x12, 6 ; 18
> 
>  SCLK_LOW;
> 21a: 82 b3  in r24, 0x12 ; 18
> 21c: 82 23  and r24, r18
> 21e: 82 bb  out 0x12, r24 ; 18
> 
>  CS_HIGH; // disable all ADCs
> 220: 97 9a  sbi 0x12, 7 ; 18
> }
> 222: 08 95  ret
> 
> 
> As you can see, all the SDO_*, SCLK_*, and CS_* 'instructions' 
> compile fine except the SCLK_LOW macro which takes 3 or 4 
> instructions rather than just one...
> 
> SCLK_LOW;
> 208: 2f eb  ldi r18, 0xBF ; 191
> 20a: 82 b3  in r24, 0x12 ; 18
> 20c: 82 23  and r24, r18
> 20e: 82 bb  out 0x12, r24 ; 18
> 
> I suspect the compiler is getting this wrong (e.g. not optimising
> consistently), or is it something I am doing wrong?
> 
> Thanks in advance.
> 
> Rob
> avr-gcc-list at http://avr1.org 


avr-gcc-list at http://avr1.org