AW: [avr-gcc-list] ADC anomaly

[Haase Bjoern (EW-BEU/PMT) *]

Hi,

Jörg Wunsch wrote
>Just since nobody else mentioned it so far: are you sure you don't
>`overdrive' the clock frequency of your ADC?  If the clock is too
>high, it's not that it wouldn't work at all, but the accuracy goes
>down the stairs.  

... I have just finished some thorough tests of the atmega ADC. My experience 
is, that overclocking indeed results in some weird results. The problem, 
however, seems to be less severe, when using constant input voltages.

I have just finished some ADC tests concerning overclocking and differential 
nonlinearity around VREF/2. Here are measurement results for one, (single) 
atmega160 device (DNL for fixed, constant input voltage):

ADC clock [Hz]          Average DNL     [LSB]           Maximum observed DNL 
[LSB]
62k5                            0,043                   0,06 
250k                            0,044                           0,06
500k                            0,054                           0,13
1 M                             0,13                            0,31
2 M                             Missing codes. Bit #0 is no longer reliable.


Problems, however, arise when using non-constant input voltages. Here I have 
observed no serious deviations (i.e. constant measurement results) using clocks 
up to 500 kHz. Errors can jump up to values 15 (!) LSB and more when using a 
ADC clock of 1 MHz.

>(Someone reported in a German newsgroup that the ADC
>can even be run at several MHz if only 6 bits of accuracy are
>desired.)

Seems that my measurements independently reproduce the observation of others.

Concerning Douglas Dotson's original problem: 

In order to find out whether the ADC clock has an influence, it might help to 
isolate the problem by comparing results for different ADC clocks. Whithin the 
safe (specified) region changes should remain within +-1 LSB.

Yours,

 Björn Haase