PR18251 is related to block moves of data. This is a QImode (byte) operation.
The bug you are reporting is an SImode (32 bit) move from memory (post inc) to register. It may be related - but it is not the same.
Still a bug is a bug.
I will look at RTL code to see what is happening. Normally the problem is related to the pointer reg "Z" when X and Y are also used up. What I cant see yet is why R26,R27 are used up. I do know that asm statement tend to confuse gcc. You might want to try specifying "z" as input and output with a "+" or tell it "z" is destroyed . this will make gcc change code and sometimes it works!
Greetings,
Bug 18251 as discussed in
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=18251
is afaict not fully resolved in gcc HEAD as of today. It compiles on
3.4.3 with no problems so this appears to be a 4.x regression.
I have not filed a bug report with gcc bugzilla as I have never done
this and I don't want to bug the developers with stupid errors on my
part. The code snippet used to be part of an MD5 transform function
but I have stripped it down to the point where it is still valid C
code but does not do anything useful any more. In this state removing
any of the remaining lines usually prevents the ICE from occurring,
most notably the LPM macro (taken from avr-libc HEAD).
Shall I file this with bugzilla? And more importantly, what's causing
it and how can I fix this?
Cheers,
Stephan
The code snippet below yields the following ICE:
$ avr-gcc -Os -mmcu=atmega162 -c test.c
test.c: In function 'test':
test.c:46: error: unable to find a register to spill in class 'POINTER_REGS'
test.c:46: error: this is the insn:
(insn 18 115 20 0 (set (reg/v:SI 56 [ a ])
(mem:SI (post_inc:HI (reg/f:HI 22 r22 [orig:59 D.1226 ] [59])) [2 S4
A8])) 14 {*movsi} (insn_list:REG_DEP_TRUE 115 (nil))
(expr_list:REG_INC (reg/f:HI 22 r22 [orig:59 D.1226 ] [59])
(nil)))
test.c:46: internal compiler error: in spill_failure, at reload1.c:1897
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.
Compiler version:
$ avr-gcc -v
Using built-in specs.
Target: avr
Configured with: ../configure --target=avr --prefix=/home/eisvogel/avr
--enable-languages=c,c++ --disable-nls
Thread model: single
gcc version 4.1.0 20050422 (experimental)
--- TEST CASE START ---
#define __LPM_enhanced__(addr) \
({ \
unsigned int __addr16 = (unsigned int)(addr); \
unsigned char __result; \
__asm__ \
( \
"lpm %0, Z" "\n\t" \
: "=r" (__result) \
: "z" (__addr16) \
); \
__result; \
})
void test ( unsigned long *state )
{
unsigned long a, b, c, d, temp;
unsigned char i;
a = state[0];
b = state[1];
c = state[2];
d = state[3];
for ( i=0 ; i<2 ; i++ ) {
temp = a;
switch ( i ) {
case 1: temp += (((b) & (d)) | ((c) & (~d)));
}
temp += __LPM_enhanced__( 0 );
a = d;
d = c;
c = b;
b = temp;
}
state[0] += a;
state[1] += b;
state[2] += c;
state[3] += d;
}
--- TEST CASE END ---
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