[avr-gcc-list] Compiler generates much overhead and "stupid" code sometimes....

[AndreasClaudius . Vogel]

Hello !
I've the following problem (?):

I wanna have a while loop, wich is waiting
until the Timer overflow flag is set (see C-Code below).
Viewing this in an dissassembler (AVR
Studio), the compiler seems to make very very much overhead !

Also, the .lst and the .lss files differ.



1.question: why the files differ?
2.question: why the compiler needs 10
instructions if optimize is off?
         
    it seems, the compiler shifts a constant until Bit 6 is set....
         
    with opt = 2, the compiler generates 3 assembler instructions.....


Thanks, Andreas


C-Code:

#include <avr/io.h>
void Wait_us(unsigned char  TimeToWait)
{
        TCCR2=0;
               
               
       // Stop Timer 2
        TCNT2=0xFF
- TimeToWait;        // Set Timer 2
        TIFR
|= (1<< TOV2);            
           // Clr Overflow
Flag
        TCCR2=(1<<CS21);
               
       // Set Timer 2 = MCLK / 8 => 1µs
/ Tick
        while(!(TIFR
& 0x40));              
 // Wait until overflow
        TCCR2=0;
               
               
       // Stop Timer 2
}
void main(void)
{
Wait_us(10);
}





// *** LST File *** //

  15:While.c      
****         while(!(TIFR & 0x40));  
             // Wait
until overflow
  94        
              .LM6:
  95 0036 8091 5600    
            lds r24,86
  96 003a 9927      
               clr
r25
  97 003c 0024      
               clr
__tmp_reg__
  98 003e 880F      
               lsl
r24
  99 0040 991F      
               rol
r25
 100 0042 001C      
               rol
__tmp_reg__
 101 0044 880F      
               lsl
r24
 102 0046 991F      
               rol
r25
 103 0048 001C      
               rol
__tmp_reg__
 104 004a 892F      
               mov
r24,r25
 105 004c 902D      
               mov
r25,__tmp_reg__
 106 004e 8170      
               andi
r24,lo8(1)
 107 0050 9070      
               andi
r25,hi8(1)
 108 0052 0097      
               sbiw
r24,0
 109 0054 09F4      
               brne
.L3
 110 0056 EFCF      
               rjmp
.L2
 111        
              .L3:


// *** LSS File ***///

  16:While.c      
****         TCCR2=0;

        while(!(TIFR
& 0x40));              
 // Wait until overflow
     100:    
   80 91 56 00         lds
       r24, 0x0056
     104:    
   99 27              
eor        r25, r25
     106:    
   00 24              
eor        r0, r0
     108:    
   88 0f              
add        r24, r24
     10a:    
   99 1f              
adc        r25, r25
     10c:    
   00 1c              
adc        r0, r0
     10e:    
   88 0f              
add        r24, r24
     110:    
   99 1f              
adc        r25, r25
     112:    
   00 1c              
adc        r0, r0
     114:    
   89 2f              
mov        r24, r25
     116:    
   90 2d              
mov        r25, r0
     118:    
   81 70              
andi        r24, 0x01    
   ; 1
     11a:    
   90 70              
andi        r25, 0x00    
   ; 0
     11c:    
   00 97              
sbiw        r24, 0x00    
   ; 0
     11e:    
   09 f4              
brne        .+2      
       ; 0x122
     120:    
   ef cf              
rjmp        .-34      
      ; 0x100
        TCCR2=0;
               
               
       // Stop Timer 2