Re: [avr-gcc-list] ATmega16 ADC at High Clock Rates

[Keith Gudger]

In our case, the max clock was 1 MHz.  Above ~250 KHz you drop to 9 bits,
above 500 KHz you somewhere between 8 and 9, but that was fine for us.

Keith

On Tue, 16 Aug 2005, User Tomdean wrote:

> The ATmega16 datasheet states, in part,
> 
>   By default, the successive approximation circuitry requires an input
>   clock frequency between 50 kHz and 200 kHz to get maximum
>   resoultion.  If a lower resolution than 10 bits is needed, the input
>   clock frequency to the ADC can be higher than 200 kHz to get a
>   higher sample rate.
> 
> The datasheet does not specify the reduction in resolution due to a
> higher clock rate.
> 
> Before I measure, does anyone know the reduction in resoultion, say,
> at 1 mHz?  2 mHz?
> 
> tomdean
> 
> 
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