Re: [avr-gcc-list] 32-bits time

[Dmitry K.]

On Thursday 13 October 2005 09:06, Eric wrote:
> Between the first TCNT1L read and the second, the counter is going to be
> incremented, so the comparison will failed each time, isn't it ?
[...]
> > I have implemented a 32-bits time information using the code below.
> > Timer1 is incremented using internal clock, prescaler=1; SIG_OVERFLOW
> > interrupt is used to increment a variable used to complete the 16-bits
[...]

Sorry, I have miss that prescaler is 1.
More exactly:

#define __SFR_OFFSET  0
        in      r0, TCNT1L      ; TEMP loading
1:      in      r0, TCNT1H
        lds     r24, hiword_time
        lds     r25, hiword_time + 1
        in      r22, TCNT1L
        in      r23, TCNT1H
        cp      r23, r0
        brne    1b
        ret

Loop length is optimized.
(SREG.I always 1 is implied.)

Regards.