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RE: [avr-gcc-list] ATmega8515 Interrupt Timing
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From: |
Nigel Winterbottom |
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Subject: |
RE: [avr-gcc-list] ATmega8515 Interrupt Timing |
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Date: |
Sat, 29 Jul 2006 22:35:11 +0100 |
> From:
> address@hidden
> [mailto:avr-gcc-list-bounces+nigel=n-winterbottom.freeserve.co
> address@hidden
> .org]On Behalf Of User Tomdean
> Sent: Saturday, July 29, 2006 4:22 PM
> To: address@hidden
> Subject: Re: [avr-gcc-list] ATmega8515 Interrupt Timing
>
>
> Look at the listing, particularly the dump. I have accounted for all
> the instructions. The timing is stable, no 125nsec jumps, so the same
> thing is happening every cycle.
>
> What I can't account for is the extra cycle at the start of the ISR.
>
> tomdean
I think you are seeing the effect of I/O synchronisation. It will take 1
cycle for any change on an I/O pin to be reflected in the PIN register.
Nigel