Re: [avr-gcc-list] ATmega8515 Interrupt Timing

[Marek Michalkiewicz]

On Sat, Jul 29, 2006 at 05:39:57PM -0700, User Tomdean wrote:

> ALE happens at the 2/3 point in the clk period.  The output change is
> at the 1/3 point in the clock period.

Could you check what happens at lower clock frequencies?  Are these
delays constant, or always 1/3 or 2/3 of the clock period?  Some
people suspect that AVR chips include a PLL clock multiplier, to
give the appearance of "single-cycle" instruction execution...

Some time ago, a restriction on sudden clock frequency changes (no
more than 2% between clock periods) was added to many datasheets -
another reason to suspect a PLL (in a fully static design without
a PLL, such sudden changes shouldn't cause any problems as long as
minimum clock period and high/low time are within specifications).

Thanks,
Marek