Re: [avr-gcc-list] Fine Tuning code timings

[Mark Litwack]

On Wed, 2 Jan 2008 10:10:28 -0600
David Kelly <address@hidden> wrote:
> On Wed, Jan 02, 2008 at 10:59:05AM -0500, Mark Litwack
> wrote:
> > 
> > One other way to approach this without having to deal
> > with the fixed latency of the Tx ISR and any other
> > interfering ISRs is to use the Compare Match Output bit
> > on the timer as the Tx bit.  It's close to what you're
> > doing, but using the output bit allows the counter
> > hardware to autonomously land the Tx bit in exactly the
> > right position.
> > 
> > The code is a little tricky, but the basic strategy is
> > to repeatedly set up the OCR and COM registers so that
> > the output pin gets set to 0 or 1 at the *next* bit
> > time.
> > 
> > In addition to setting the Tx pin, at each next bit
> > time a Tx ISR is called to set up the OCR and COM
> > registers again for the next bit.  The OCR is loaded
> > with OCR + BIT_TIME, and the COM is set up to clear or
> > set the output bit (Tx) depending on the next Tx bit
> > value.
> 
> There is a mode where one only writes the BIT_TIME in the
> OCRx register once and the paired timer resets to 0 with
> the output bit change. So all you have to do in the ISR
> is to decide which output value is to be sent next. The
> transmitted timing will be as precise as your timer.
> 

True, however I'm also using the same timer for Rx timing
(OCRA for Tx timing and OCRB for Rx timing), and also using
the same timer's overflow interrupt for periodic threads.

I'm forced to have an ISR anyway to set up the next bit in
COMA, so with a few extra instructions to keep reloading the
OCR registers I get triple duty out of one timer.  (You can
never have enough timers... or UARTs for that matter...)

-mark