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[avr-gcc-list] Upgraded and re-compiled a current project and a function
|
From: |
Ray Hurst |
|
Subject: |
[avr-gcc-list] Upgraded and re-compiled a current project and a function was converted to in-line and a function. |
|
Date: |
Fri, 18 Apr 2008 15:57:17 -0700 |
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User-agent: |
Thunderbird 2.0.0.12 (Windows/20080213) |
I just installed WinAvr-20080411 and re-compiled a recent project (lab4a).
I was surprised that the code increased by almost 400 bytes (lab4b).
Looking into the reason I see that the compiler generated my EEPROM_read
function and then started generating the function in-line in all of the
places I called it.
Any reason for this?
Ray
lab4a.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000004b4 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000104 00800060 000004b4 00000528 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000086 00800164 000005b8 0000062c 2**0
ALLOC
3 .stab 00000378 00000000 00000000 0000062c 2**2
CONTENTS, READONLY, DEBUGGING
4 .stabstr 0000005f 00000000 00000000 000009a4 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_aranges 00000020 00000000 00000000 00000a03 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_pubnames 000001d6 00000000 00000000 00000a23 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_info 00000613 00000000 00000000 00000bf9 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_abbrev 0000023b 00000000 00000000 0000120c 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_line 000005ec 00000000 00000000 00001447 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_frame 00000160 00000000 00000000 00001a34 2**2
CONTENTS, READONLY, DEBUGGING
11 .debug_str 00000265 00000000 00000000 00001b94 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_loc 0000016d 00000000 00000000 00001df9 2**0
CONTENTS, READONLY, DEBUGGING
13 .debug_ranges 00000090 00000000 00000000 00001f66 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 10 c0 rjmp .+32 ; 0x22 <__ctors_end>
2: 2a c0 rjmp .+84 ; 0x58 <__bad_interrupt>
4: 29 c0 rjmp .+82 ; 0x58 <__bad_interrupt>
6: 28 c0 rjmp .+80 ; 0x58 <__bad_interrupt>
8: 27 c0 rjmp .+78 ; 0x58 <__bad_interrupt>
a: 26 c0 rjmp .+76 ; 0x58 <__bad_interrupt>
c: 35 c1 rjmp .+618 ; 0x278 <__vector_6>
e: 24 c0 rjmp .+72 ; 0x58 <__bad_interrupt>
10: 23 c0 rjmp .+70 ; 0x58 <__bad_interrupt>
12: 6d c1 rjmp .+730 ; 0x2ee <__vector_9>
14: 21 c0 rjmp .+66 ; 0x58 <__bad_interrupt>
16: 20 c0 rjmp .+64 ; 0x58 <__bad_interrupt>
18: 1f c0 rjmp .+62 ; 0x58 <__bad_interrupt>
1a: 1e c0 rjmp .+60 ; 0x58 <__bad_interrupt>
1c: 1d c0 rjmp .+58 ; 0x58 <__bad_interrupt>
1e: 1c c0 rjmp .+56 ; 0x58 <__bad_interrupt>
20: 1b c0 rjmp .+54 ; 0x58 <__bad_interrupt>
00000022 <__ctors_end>:
22: 11 24 eor r1, r1
24: 1f be out 0x3f, r1 ; 63
26: cf e5 ldi r28, 0x5F ; 95
28: d2 e0 ldi r29, 0x02 ; 2
2a: de bf out 0x3e, r29 ; 62
2c: cd bf out 0x3d, r28 ; 61
0000002e <__do_copy_data>:
2e: 11 e0 ldi r17, 0x01 ; 1
30: a0 e6 ldi r26, 0x60 ; 96
32: b0 e0 ldi r27, 0x00 ; 0
34: e4 eb ldi r30, 0xB4 ; 180
36: f4 e0 ldi r31, 0x04 ; 4
38: 02 c0 rjmp .+4 ; 0x3e <__SP_H__>
0000003a <.do_copy_data_loop>:
3a: 05 90 lpm r0, Z+
3c: 0d 92 st X+, r0
0000003e <.do_copy_data_start>:
3e: a4 36 cpi r26, 0x64 ; 100
40: b1 07 cpc r27, r17
42: d9 f7 brne .-10 ; 0x3a <.do_copy_data_loop>
00000044 <__do_clear_bss>:
44: 11 e0 ldi r17, 0x01 ; 1
46: a4 e6 ldi r26, 0x64 ; 100
48: b1 e0 ldi r27, 0x01 ; 1
4a: 01 c0 rjmp .+2 ; 0x4e <.do_clear_bss_start>
0000004c <.do_clear_bss_loop>:
4c: 1d 92 st X+, r1
0000004e <.do_clear_bss_start>:
4e: aa 3e cpi r26, 0xEA ; 234
50: b1 07 cpc r27, r17
52: e1 f7 brne .-8 ; 0x4c <.do_clear_bss_loop>
54: 83 d1 rcall .+774 ; 0x35c <main>
56: 2d c2 rjmp .+1114 ; 0x4b2 <_exit>
00000058 <__bad_interrupt>:
58: d3 cf rjmp .-90 ; 0x0 <__heap_end>
0000005a <weAreDead>:
/* Abort routine */
void
weAreDead( void )
{
cli(); /* disable global interrupts */
5a: f8 94 cli
PORTD = ABORTED; /* set PORTD bit 6 - ABORTED */
5c: 8f eb ldi r24, 0xBF ; 191
5e: 82 bb out 0x12, r24 ; 18
60: ff cf rjmp .-2 ; 0x60 <weAreDead+0x6>
00000062 <EEPROM_read>:
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
62: e1 99 sbic 0x1c, 1 ; 28
64: fe cf rjmp .-4 ; 0x62 <EEPROM_read>
;
/* setup address register */
EEAR = uiAddress;
66: 9f bb out 0x1f, r25 ; 31
68: 8e bb out 0x1e, r24 ; 30
cli(); /* disable global interrupts */
6a: f8 94 cli
/* start the EEPROM read process */
EECR |= _BV(EERE);
6c: e0 9a sbi 0x1c, 0 ; 28
/* return the data from the data register */
sei(); /* enable global interrupts */
6e: 78 94 sei
return EEDR;
70: 8d b3 in r24, 0x1d ; 29
}
72: 90 e0 ldi r25, 0x00 ; 0
74: 08 95 ret
00000076 <EEPROM_write>:
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
76: e1 99 sbic 0x1c, 1 ; 28
78: fe cf rjmp .-4 ; 0x76 <EEPROM_write>
;
/* setup address and data registers */
EEAR = uiAddress;
7a: 9f bb out 0x1f, r25 ; 31
7c: 8e bb out 0x1e, r24 ; 30
EEDR = ucData;
7e: 6d bb out 0x1d, r22 ; 29
cli(); /* disable global interrupts */
80: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
82: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
84: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
86: 78 94 sei
88: 08 95 ret
0000008a <EEPROM_verifyHeader>:
Function : EEPROM_verifyHeader
Description : read and validate the EEPROM header
*/
uint8_t
EEPROM_verifyHeader( P_EEPROM_HEADER pEEpromHeader )
{
8a: 0f 93 push r16
8c: 1f 93 push r17
8e: 8c 01 movw r16, r24
uint8_t dataValid = FALSE; /* assume the EEPROM data is invalid */
/* read signature bytes */
pEEpromHeader->signature = EEPROM_read( EEPROM_ADDRESS_SIGNATURE );
90: 80 e0 ldi r24, 0x00 ; 0
92: 90 e0 ldi r25, 0x00 ; 0
94: e6 df rcall .-52 ; 0x62 <EEPROM_read>
96: f8 01 movw r30, r16
98: 80 83 st Z, r24
pEEpromHeader->count = EEPROM_read( EEPROM_ADDRESS_COUNT );
9a: 81 e0 ldi r24, 0x01 ; 1
9c: 90 e0 ldi r25, 0x00 ; 0
9e: e1 df rcall .-62 ; 0x62 <EEPROM_read>
a0: f8 01 movw r30, r16
a2: 81 83 std Z+1, r24 ; 0x01
a4: 90 e0 ldi r25, 0x00 ; 0
a6: 80 81 ld r24, Z
a8: 8a 35 cpi r24, 0x5A ; 90
aa: 09 f4 brne .+2 ; 0xae
<EEPROM_verifyHeader+0x24>
ac: 91 e0 ldi r25, 0x01 ; 1
if( EEPROM_DATA_SIGNATURE == pEEpromHeader->signature )
dataValid = TRUE;
return dataValid;
}
ae: 89 2f mov r24, r25
b0: 90 e0 ldi r25, 0x00 ; 0
b2: 1f 91 pop r17
b4: 0f 91 pop r16
b6: 08 95 ret
000000b8 <EEPROM_initializeHeader>:
Description : write EEPROM header
*/
void
EEPROM_initializeHeader( void )
{
EEPROM_write( EEPROM_ADDRESS_SIGNATURE, EEPROM_DATA_SIGNATURE );
b8: 6a e5 ldi r22, 0x5A ; 90
ba: 80 e0 ldi r24, 0x00 ; 0
bc: 90 e0 ldi r25, 0x00 ; 0
be: db df rcall .-74 ; 0x76 <EEPROM_write>
EEPROM_write( EEPROM_ADDRESS_COUNT, 0 );
c0: 60 e0 ldi r22, 0x00 ; 0
c2: 81 e0 ldi r24, 0x01 ; 1
c4: 90 e0 ldi r25, 0x00 ; 0
c6: d7 df rcall .-82 ; 0x76 <EEPROM_write>
c8: 08 95 ret
000000ca <crlf>:
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
ca: 5d 9b sbis 0x0b, 5 ; 11
cc: fe cf rjmp .-4 ; 0xca <crlf>
UDR = c;
ce: 8d e0 ldi r24, 0x0D ; 13
d0: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
d2: 5d 9b sbis 0x0b, 5 ; 11
d4: fe cf rjmp .-4 ; 0xd2 <crlf+0x8>
UDR = c;
d6: 8a e0 ldi r24, 0x0A ; 10
d8: 8c b9 out 0x0c, r24 ; 12
da: 08 95 ret
000000dc <bin2AsciiHex>:
This function converts a the lower 4 bits of a binary byte into an
ASCII hex character
*/
uint8_t
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
dc: 8f 70 andi r24, 0x0F ; 15
if( byte > 9 )
de: 8a 30 cpi r24, 0x0A ; 10
e0: 08 f0 brcs .+2 ; 0xe4 <bin2AsciiHex+0x8>
byte += 7;
e2: 89 5f subi r24, 0xF9 ; 249
e4: 80 5d subi r24, 0xD0 ; 208
byte += '0';
return byte;
}
e6: 90 e0 ldi r25, 0x00 ; 0
e8: 08 95 ret
000000ea <usart_putchar>:
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
ea: 5d 9b sbis 0x0b, 5 ; 11
ec: fe cf rjmp .-4 ; 0xea <usart_putchar>
UDR = c;
ee: 8c b9 out 0x0c, r24 ; 12
f0: 08 95 ret
000000f2 <io_printString>:
Output a string pointed to by s to the standard output device.
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
f2: fc 01 movw r30, r24
f4: 04 c0 rjmp .+8 ; 0xfe <io_printString+0xc>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
f6: 5d 9b sbis 0x0b, 5 ; 11
f8: fe cf rjmp .-4 ; 0xf6 <io_printString+0x4>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
fa: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
fc: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
fe: 80 81 ld r24, Z
100: 88 23 and r24, r24
102: c9 f7 brne .-14 ; 0xf6 <io_printString+0x4>
104: 08 95 ret
00000106 <io_putchar>:
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
106: 5d 9b sbis 0x0b, 5 ; 11
108: fe cf rjmp .-4 ; 0x106 <io_putchar>
UDR = c;
10a: 8c b9 out 0x0c, r24 ; 12
10c: 08 95 ret
0000010e <io_puts>:
The terminating null byte is not written.
*/
void
io_puts ( const char *s )
{
io_printString( s );
10e: f1 df rcall .-30 ; 0xf2 <io_printString>
crlf();
110: dc df rcall .-72 ; 0xca <crlf>
112: 08 95 ret
00000114 <io_putHex>:
Description:
Convert a byte value into two ASCII hex characters and output
them to the standard output device.
*/
void
io_putHex( char c )
{
114: 1f 93 push r17
116: 18 2f mov r17, r24
io_putchar( bin2AsciiHex(c >> 4) );
118: 82 95 swap r24
11a: 8f 70 andi r24, 0x0F ; 15
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
11c: 5d 9b sbis 0x0b, 5 ; 11
11e: fe cf rjmp .-4 ; 0x11c <io_putHex+0x8>
Convert a byte value into two ASCII hex characters and output
them to the standard output device.
*/
void
io_putHex( char c )
{
io_putchar( bin2AsciiHex(c >> 4) );
120: dd df rcall .-70 ; 0xdc <bin2AsciiHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
122: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
124: 5d 9b sbis 0x0b, 5 ; 11
126: fe cf rjmp .-4 ; 0x124 <io_putHex+0x10>
*/
void
io_putHex( char c )
{
io_putchar( bin2AsciiHex(c >> 4) );
io_putchar( bin2AsciiHex(c) );
128: 81 2f mov r24, r17
12a: d8 df rcall .-80 ; 0xdc <bin2AsciiHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
12c: 8c b9 out 0x0c, r24 ; 12
12e: 1f 91 pop r17
130: 08 95 ret
00000132 <displayData_formatted>:
Description:
Display data as ASCII hex, neatly formatted 16 bytes per line
*/
void
displayData_formatted ( uint16_t index, uint8_t data )
{
132: 1f 93 push r17
134: cf 93 push r28
136: df 93 push r29
138: ec 01 movw r28, r24
13a: 16 2f mov r17, r22
if ( 0 == (index % 16) )
13c: 8f 70 andi r24, 0x0F ; 15
13e: 90 70 andi r25, 0x00 ; 0
140: 89 2b or r24, r25
142: 51 f4 brne .+20 ; 0x158
<displayData_formatted+0x26>
{
crlf();
144: c2 df rcall .-124 ; 0xca <crlf>
io_putHex( index >> 8 );
146: 8d 2f mov r24, r29
148: 99 27 eor r25, r25
14a: e4 df rcall .-56 ; 0x114 <io_putHex>
io_putHex( index );
14c: 8c 2f mov r24, r28
14e: e2 df rcall .-60 ; 0x114 <io_putHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
150: 5d 9b sbis 0x0b, 5 ; 11
152: fe cf rjmp .-4 ; 0x150
<displayData_formatted+0x1e>
UDR = c;
154: 8a e3 ldi r24, 0x3A ; 58
156: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
158: 5d 9b sbis 0x0b, 5 ; 11
15a: fe cf rjmp .-4 ; 0x158
<displayData_formatted+0x26>
UDR = c;
15c: 80 e2 ldi r24, 0x20 ; 32
15e: 8c b9 out 0x0c, r24 ; 12
io_putHex( index >> 8 );
io_putHex( index );
io_putchar( ':' );
}
io_putchar( ' ' );
io_putHex( data );
160: 81 2f mov r24, r17
162: d8 df rcall .-80 ; 0x114 <io_putHex>
164: df 91 pop r29
166: cf 91 pop r28
168: 1f 91 pop r17
16a: 08 95 ret
0000016c <dumpDataMemory>:
Description:
Display the data memory (512 bytes)
*/
void
dumpDataMemory( void )
{
16c: cf 93 push r28
16e: df 93 push r29
uint16_t i;
uint8_t *dataPtr = (uint8_t *)0x60;
crlf();
170: ac df rcall .-168 ; 0xca <crlf>
io_puts( "DM Dump:");
172: 80 e6 ldi r24, 0x60 ; 96
174: 90 e0 ldi r25, 0x00 ; 0
176: cb df rcall .-106 ; 0x10e <io_puts>
178: c0 e6 ldi r28, 0x60 ; 96
17a: d0 e0 ldi r29, 0x00 ; 0
17c: ce 01 movw r24, r28
17e: 80 56 subi r24, 0x60 ; 96
180: 90 40 sbci r25, 0x00 ; 0
for( i = 0; i < 512; i++ )
displayData_formatted( i, *dataPtr++ );
182: 69 91 ld r22, Y+
184: d6 df rcall .-84 ; 0x132 <displayData_formatted>
uint8_t *dataPtr = (uint8_t *)0x60;
crlf();
io_puts( "DM Dump:");
for( i = 0; i < 512; i++ )
186: 82 e0 ldi r24, 0x02 ; 2
188: c0 36 cpi r28, 0x60 ; 96
18a: d8 07 cpc r29, r24
18c: b9 f7 brne .-18 ; 0x17c <dumpDataMemory+0x10>
18e: df 91 pop r29
190: cf 91 pop r28
192: 08 95 ret
00000194 <EEPROM_displayHeader>:
Description : display the EEPROM header
*/
void
EEPROM_displayHeader( P_EEPROM_HEADER pEEpromHeader )
{
crlf();
194: 9a df rcall .-204 ; 0xca <crlf>
io_printString( "Signature: 0x" );
196: 89 e6 ldi r24, 0x69 ; 105
198: 90 e0 ldi r25, 0x00 ; 0
19a: ab df rcall .-170 ; 0xf2 <io_printString>
io_putHex( eePromHeader.signature );
19c: 80 91 e7 01 lds r24, 0x01E7
1a0: b9 df rcall .-142 ; 0x114 <io_putHex>
crlf();
1a2: 93 df rcall .-218 ; 0xca <crlf>
io_printString( "Count: 0x" );
1a4: 87 e7 ldi r24, 0x77 ; 119
1a6: 90 e0 ldi r25, 0x00 ; 0
1a8: a4 df rcall .-184 ; 0xf2 <io_printString>
io_putHex( eePromHeader.count );
1aa: 80 91 e8 01 lds r24, 0x01E8
1ae: b2 df rcall .-156 ; 0x114 <io_putHex>
crlf();
1b0: 8c df rcall .-232 ; 0xca <crlf>
1b2: 08 95 ret
000001b4 <EEPROM_record>:
Description : store USART data received into EEPROM
*/
void
EEPROM_record( void )
{
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
1b4: 87 ee ldi r24, 0xE7 ; 231
1b6: 91 e0 ldi r25, 0x01 ; 1
1b8: 68 df rcall .-304 ; 0x8a <EEPROM_verifyHeader>
1ba: 81 30 cpi r24, 0x01 ; 1
1bc: 89 f5 brne .+98 ; 0x220 <EEPROM_record+0x6c>
EEPROM_displayHeader( &eePromHeader );
1be: 87 ee ldi r24, 0xE7 ; 231
1c0: 91 e0 ldi r25, 0x01 ; 1
1c2: e8 df rcall .-48 ; 0x194 <EEPROM_displayHeader>
1c4: 21 c0 rjmp .+66 ; 0x208 <EEPROM_record+0x54>
while( dataIndex_write != dataIndex_read )
{
if ( EEPROM_DATA_COUNT_MAX == eePromHeader.count )
1c6: 80 91 e8 01 lds r24, 0x01E8
1ca: 8e 3f cpi r24, 0xFE ; 254
1cc: 49 f4 brne .+18 ; 0x1e0 <EEPROM_record+0x2c>
{
crlf();
1ce: 7d df rcall .-262 ; 0xca <crlf>
io_puts( "EEPROM full!" );
1d0: 81 e8 ldi r24, 0x81 ; 129
1d2: 90 e0 ldi r25, 0x00 ; 0
1d4: 9c df rcall .-200 ; 0x10e <io_puts>
dataIndex_write = dataIndex_read; /* discard remaining
characters */
1d6: 80 91 e6 01 lds r24, 0x01E6
1da: 80 93 e9 01 sts 0x01E9, r24
1de: 1a c0 rjmp .+52 ; 0x214 <EEPROM_record+0x60>
break;
}
else
{
EEPROM_write( EEPROM_ADDRESS_DATA + eePromHeader.count,
dataBuffer[dataIndex_write] );
1e0: f0 e0 ldi r31, 0x00 ; 0
1e2: ea 59 subi r30, 0x9A ; 154
1e4: fe 4f sbci r31, 0xFE ; 254
1e6: 90 e0 ldi r25, 0x00 ; 0
1e8: 60 81 ld r22, Z
1ea: 02 96 adiw r24, 0x02 ; 2
1ec: 44 df rcall .-376 ; 0x76 <EEPROM_write>
eePromHeader.count++;
1ee: 80 91 e8 01 lds r24, 0x01E8
1f2: 8f 5f subi r24, 0xFF ; 255
1f4: 80 93 e8 01 sts 0x01E8, r24
INCREMENT_DATA_INDEX_WRITE;
1f8: 80 91 e9 01 lds r24, 0x01E9
1fc: 90 e0 ldi r25, 0x00 ; 0
1fe: 01 96 adiw r24, 0x01 ; 1
200: 8f 77 andi r24, 0x7F ; 127
202: 90 70 andi r25, 0x00 ; 0
204: 80 93 e9 01 sts 0x01E9, r24
EEPROM_record( void )
{
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
EEPROM_displayHeader( &eePromHeader );
while( dataIndex_write != dataIndex_read )
208: e0 91 e9 01 lds r30, 0x01E9
20c: 80 91 e6 01 lds r24, 0x01E6
210: e8 17 cp r30, r24
212: c9 f6 brne .-78 ; 0x1c6 <EEPROM_record+0x12>
eePromHeader.count++;
INCREMENT_DATA_INDEX_WRITE;
}
}
/* update EEPROM data log counter */
EEPROM_write( EEPROM_ADDRESS_COUNT, eePromHeader.count );
214: 60 91 e8 01 lds r22, 0x01E8
218: 81 e0 ldi r24, 0x01 ; 1
21a: 90 e0 ldi r25, 0x00 ; 0
21c: 2c df rcall .-424 ; 0x76 <EEPROM_write>
21e: 08 95 ret
}
else
{
crlf();
220: 54 df rcall .-344 ; 0xca <crlf>
io_puts( "EEPROM invalid!" );
222: 8e e8 ldi r24, 0x8E ; 142
224: 90 e0 ldi r25, 0x00 ; 0
226: 73 df rcall .-282 ; 0x10e <io_puts>
228: 08 95 ret
0000022a <EEPROM_playback>:
Function : EEPROM_playback
Description : send each byte in the EEPROM to the USART transmitter
*/
void
EEPROM_playback( void )
{
22a: 0f 93 push r16
22c: 1f 93 push r17
22e: cf 93 push r28
230: df 93 push r29
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
232: 87 ee ldi r24, 0xE7 ; 231
234: 91 e0 ldi r25, 0x01 ; 1
236: 29 df rcall .-430 ; 0x8a <EEPROM_verifyHeader>
238: 81 30 cpi r24, 0x01 ; 1
23a: a9 f4 brne .+42 ; 0x266 <__stack+0x7>
uint8_t i, j, data;
EEPROM_displayHeader( &eePromHeader );
23c: 87 ee ldi r24, 0xE7 ; 231
23e: 91 e0 ldi r25, 0x01 ; 1
240: a9 df rcall .-174 ; 0x194 <EEPROM_displayHeader>
242: c0 e0 ldi r28, 0x00 ; 0
244: d0 e0 ldi r29, 0x00 ; 0
246: 07 c0 rjmp .+14 ; 0x256 <EEPROM_playback+0x2c>
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
{
data = EEPROM_read( EEPROM_ADDRESS_DATA + i );
248: 10 e0 ldi r17, 0x00 ; 0
24a: c8 01 movw r24, r16
24c: 02 96 adiw r24, 0x02 ; 2
24e: 09 df rcall .-494 ; 0x62 <EEPROM_read>
displayData_formatted( j, data );
250: 68 2f mov r22, r24
252: c8 01 movw r24, r16
254: 6e df rcall .-292 ; 0x132 <displayData_formatted>
256: 0c 2f mov r16, r28
258: 21 96 adiw r28, 0x01 ; 1
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
uint8_t i, j, data;
EEPROM_displayHeader( &eePromHeader );
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
25a: 80 91 e8 01 lds r24, 0x01E8
25e: 08 17 cp r16, r24
260: 98 f3 brcs .-26 ; 0x248 <EEPROM_playback+0x1e>
{
data = EEPROM_read( EEPROM_ADDRESS_DATA + i );
displayData_formatted( j, data );
j++;
}
crlf();
262: 33 df rcall .-410 ; 0xca <crlf>
264: 04 c0 rjmp .+8 ; 0x26e <__stack+0xf>
}
else
{
crlf();
266: 31 df rcall .-414 ; 0xca <crlf>
io_puts( "EEPROM invalid!" );
268: 8e e8 ldi r24, 0x8E ; 142
26a: 90 e0 ldi r25, 0x00 ; 0
26c: 50 df rcall .-352 ; 0x10e <io_puts>
26e: df 91 pop r29
270: cf 91 pop r28
272: 1f 91 pop r17
274: 0f 91 pop r16
276: 08 95 ret
00000278 <__vector_6>:
/* Interrupt Sevice Routines (ISRs) */
/* Timer/Counter 1 Overflow Interrupt handler - 20msec interrupt */
/* Configured as an interruptable ISR */
ISR (TIMER1_OVF_vect, ISR_NOBLOCK)
{
278: 78 94 sei
27a: 1f 92 push r1
27c: 0f 92 push r0
27e: 0f b6 in r0, 0x3f ; 63
280: 0f 92 push r0
282: 11 24 eor r1, r1
284: 2f 93 push r18
286: 3f 93 push r19
288: 8f 93 push r24
28a: 9f 93 push r25
#if (DEBUG_TIMER)
PORTD = PIND ^ _BV(6); /* toggle PORTD pin 6 */
#endif
if( 0 == --delayCount ) {
28c: 80 91 63 01 lds r24, 0x0163
290: 81 50 subi r24, 0x01 ; 1
292: 80 93 63 01 sts 0x0163, r24
296: 88 23 and r24, r24
298: 09 f5 brne .+66 ; 0x2dc <__vector_6+0x64>
delayCount = DELAY_COUNT;
29a: 84 e0 ldi r24, 0x04 ; 4
29c: 80 93 63 01 sts 0x0163, r24
PORTB = ~_BV(i);
2a0: 20 91 65 01 lds r18, 0x0165
2a4: 30 e0 ldi r19, 0x00 ; 0
2a6: 81 e0 ldi r24, 0x01 ; 1
2a8: 90 e0 ldi r25, 0x00 ; 0
2aa: 02 2e mov r0, r18
2ac: 02 c0 rjmp .+4 ; 0x2b2 <__vector_6+0x3a>
2ae: 88 0f add r24, r24
2b0: 99 1f adc r25, r25
2b2: 0a 94 dec r0
2b4: e2 f7 brpl .-8 ; 0x2ae <__vector_6+0x36>
2b6: 80 95 com r24
2b8: 88 bb out 0x18, r24 ; 24
i = (i + 1) % 8; /* cycle to the next
LED */
2ba: 2f 5f subi r18, 0xFF ; 255
2bc: 3f 4f sbci r19, 0xFF ; 255
2be: 27 70 andi r18, 0x07 ; 7
2c0: 30 70 andi r19, 0x00 ; 0
2c2: 20 93 65 01 sts 0x0165, r18
/* is the switch coresponding to the lit LED closed? */
if( 0 == (PINA & _BV(i)) )
2c6: 89 b3 in r24, 0x19 ; 25
2c8: 90 e0 ldi r25, 0x00 ; 0
2ca: 02 c0 rjmp .+4 ; 0x2d0 <__vector_6+0x58>
2cc: 95 95 asr r25
2ce: 87 95 ror r24
2d0: 2a 95 dec r18
2d2: e2 f7 brpl .-8 ; 0x2cc <__vector_6+0x54>
2d4: 80 fd sbrc r24, 0
2d6: 02 c0 rjmp .+4 ; 0x2dc <__vector_6+0x64>
i = 0; /* here, the
switch is closed */
2d8: 10 92 65 01 sts 0x0165, r1
2dc: 9f 91 pop r25
2de: 8f 91 pop r24
2e0: 3f 91 pop r19
2e2: 2f 91 pop r18
2e4: 0f 90 pop r0
2e6: 0f be out 0x3f, r0 ; 63
2e8: 0f 90 pop r0
2ea: 1f 90 pop r1
2ec: 18 95 reti
000002ee <__vector_9>:
}
}
/* USART receiver full interrupt */
ISR(USART_RX_vect)
{
2ee: 1f 92 push r1
2f0: 0f 92 push r0
2f2: 0f b6 in r0, 0x3f ; 63
2f4: 0f 92 push r0
2f6: 11 24 eor r1, r1
2f8: 2f 93 push r18
2fa: 8f 93 push r24
2fc: 9f 93 push r25
2fe: ef 93 push r30
300: ff 93 push r31
/* store the USART data and exit */
dataBuffer[dataIndex_read] = UDR;
302: 80 91 e6 01 lds r24, 0x01E6
306: 90 e0 ldi r25, 0x00 ; 0
308: 2c b1 in r18, 0x0c ; 12
30a: fc 01 movw r30, r24
30c: ea 59 subi r30, 0x9A ; 154
30e: fe 4f sbci r31, 0xFE ; 254
310: 20 83 st Z, r18
INCREMENT_DATA_INDEX_READ; /* note: no buffer overflow
detection */
312: 01 96 adiw r24, 0x01 ; 1
314: 8f 77 andi r24, 0x7F ; 127
316: 90 70 andi r25, 0x00 ; 0
318: 80 93 e6 01 sts 0x01E6, r24
31c: ff 91 pop r31
31e: ef 91 pop r30
320: 9f 91 pop r25
322: 8f 91 pop r24
324: 2f 91 pop r18
326: 0f 90 pop r0
328: 0f be out 0x3f, r0 ; 63
32a: 0f 90 pop r0
32c: 1f 90 pop r1
32e: 18 95 reti
00000330 <init_system>:
void
init_system(void)
{
/* initialize global data */
dataIndex_read = dataIndex_write = 0;
330: 10 92 e9 01 sts 0x01E9, r1
334: 10 92 e6 01 sts 0x01E6, r1
#if (DEBUG_ENA_PORTD)
PORTD = INIT_PORTD;
DDRD = INIT_DDRD_DIR;
#endif
PORTB = ALL_LEDS_OFF; /* initialize PORTB */
338: 8f ef ldi r24, 0xFF ; 255
33a: 88 bb out 0x18, r24 ; 24
DDRB = INIT_DDRB_DIR; /* set PORTB direction register */
33c: 87 bb out 0x17, r24 ; 23
DDRA = INIT_DDRA_DIR; /* set PORTA direction register */
33e: 1a ba out 0x1a, r1 ; 26
/* initialize timer/counter 1 */
TCCR1A = INIT_TCCR1A;
340: 1f bc out 0x2f, r1 ; 47
TCCR1B = INIT_TCCR1B;
342: 81 e0 ldi r24, 0x01 ; 1
344: 8e bd out 0x2e, r24 ; 46
TIMSK = _BV (TOIE1);
346: 80 e8 ldi r24, 0x80 ; 128
348: 89 bf out 0x39, r24 ; 57
/* initialize USART */
UBRRL = BAUD_PRESCALE_ASYNCH_NORMAL;
34a: 87 e1 ldi r24, 0x17 ; 23
34c: 89 b9 out 0x09, r24 ; 9
UBRRH = BAUD_PRESCALE_ASYNCH_NORMAL >> 8;
34e: 10 bc out 0x20, r1 ; 32
UCSRC = USART_REG_SELECT_UCSRC | \
350: 86 e8 ldi r24, 0x86 ; 134
352: 80 bd out 0x20, r24 ; 32
USART_MODE_SELECT_ASYNCHRONOUS | \
USART_PARITY_MODE_NONE | \
USART_STOP_BITS_1 | \
USART_CHAR_SIZE_BITS_8_OR_9;
UCSRB = _BV(RXCIE) | _BV(RXEN) | _BV(TXEN); /* enable USART transmitter /
receiver */
354: 88 e9 ldi r24, 0x98 ; 152
356: 8a b9 out 0x0a, r24 ; 10
sei(); /* enable global interrupts */
358: 78 94 sei
35a: 08 95 ret
0000035c <main>:
/* main routine */
int
main( void )
{
35c: 8f 92 push r8
35e: 9f 92 push r9
360: af 92 push r10
362: bf 92 push r11
364: cf 92 push r12
366: df 92 push r13
368: ef 92 push r14
36a: ff 92 push r15
36c: 0f 93 push r16
36e: 1f 93 push r17
370: cf 93 push r28
372: df 93 push r29
374: cd b7 in r28, 0x3d ; 61
376: de b7 in r29, 0x3e ; 62
378: 22 97 sbiw r28, 0x02 ; 2
37a: 0f b6 in r0, 0x3f ; 63
37c: f8 94 cli
37e: de bf out 0x3e, r29 ; 62
380: 0f be out 0x3f, r0 ; 63
382: cd bf out 0x3d, r28 ; 61
init_system();
384: d5 df rcall .-86 ; 0x330 <init_system>
crlf();
386: a1 de rcall .-702 ; 0xca <crlf>
io_puts( "USART v0.30" ); /* if we see this, we did OK */
388: 8e e9 ldi r24, 0x9E ; 158
38a: 90 e0 ldi r25, 0x00 ; 0
38c: c0 de rcall .-640 ; 0x10e <io_puts>
crlf();
38e: 9d de rcall .-710 ; 0xca <crlf>
io_puts( "Ctrl-x - dump data memory" );
390: 8a ea ldi r24, 0xAA ; 170
392: 90 e0 ldi r25, 0x00 ; 0
394: bc de rcall .-648 ; 0x10e <io_puts>
io_puts( "Ctrl-z - start/stop data recording" );
396: 84 ec ldi r24, 0xC4 ; 196
398: 90 e0 ldi r25, 0x00 ; 0
39a: b9 de rcall .-654 ; 0x10e <io_puts>
io_puts( "Ctrl-y - playback recorded data" );
39c: 87 ee ldi r24, 0xE7 ; 231
39e: 90 e0 ldi r25, 0x00 ; 0
3a0: b6 de rcall .-660 ; 0x10e <io_puts>
/* check if EEPROM is initialized */
if( FALSE == EEPROM_verifyHeader(&eePromHeader) ) {
3a2: 87 ee ldi r24, 0xE7 ; 231
3a4: 91 e0 ldi r25, 0x01 ; 1
3a6: 71 de rcall .-798 ; 0x8a <EEPROM_verifyHeader>
3a8: 88 23 and r24, r24
3aa: 89 f4 brne .+34 ; 0x3ce <main+0x72>
/* EEPROM not initialized here */
crlf();
3ac: 8e de rcall .-740 ; 0xca <crlf>
io_printString( "EEPROM Init ... " );
3ae: 87 e0 ldi r24, 0x07 ; 7
3b0: 91 e0 ldi r25, 0x01 ; 1
3b2: 9f de rcall .-706 ; 0xf2 <io_printString>
EEPROM_initializeHeader();
3b4: 81 de rcall .-766 ; 0xb8 <EEPROM_initializeHeader>
if( FALSE == EEPROM_verifyHeader(&eePromHeader) )
3b6: 87 ee ldi r24, 0xE7 ; 231
3b8: 91 e0 ldi r25, 0x01 ; 1
3ba: 67 de rcall .-818 ; 0x8a <EEPROM_verifyHeader>
3bc: 88 23 and r24, r24
3be: 19 f4 brne .+6 ; 0x3c6 <main+0x6a>
io_puts( "FAIL" );
3c0: 88 e1 ldi r24, 0x18 ; 24
3c2: 91 e0 ldi r25, 0x01 ; 1
3c4: 02 c0 rjmp .+4 ; 0x3ca <main+0x6e>
else
io_puts( "OK" );
3c6: 8d e1 ldi r24, 0x1D ; 29
3c8: 91 e0 ldi r25, 0x01 ; 1
3ca: a1 de rcall .-702 ; 0x10e <io_puts>
crlf();
3cc: 7e de rcall .-772 ; 0xca <crlf>
3ce: 40 e2 ldi r20, 0x20 ; 32
3d0: 84 2e mov r8, r20
3d2: 41 e0 ldi r20, 0x01 ; 1
3d4: 94 2e mov r9, r20
3d6: 31 e3 ldi r19, 0x31 ; 49
3d8: a3 2e mov r10, r19
3da: 31 e0 ldi r19, 0x01 ; 1
3dc: b3 2e mov r11, r19
3de: 29 e3 ldi r18, 0x39 ; 57
3e0: c2 2e mov r12, r18
3e2: 21 e0 ldi r18, 0x01 ; 1
3e4: d2 2e mov r13, r18
3e6: 95 e5 ldi r25, 0x55 ; 85
3e8: e9 2e mov r14, r25
3ea: 91 e0 ldi r25, 0x01 ; 1
3ec: f9 2e mov r15, r25
3ee: 08 e4 ldi r16, 0x48 ; 72
3f0: 11 e0 ldi r17, 0x01 ; 1
}
while(1) {
#if (DEBUG_USART)
volatile uint16_t i = 0;
3f2: 1a 82 std Y+2, r1 ; 0x02
3f4: 19 82 std Y+1, r1 ; 0x01
if( 0 == i++ ) {
3f6: 89 81 ldd r24, Y+1 ; 0x01
3f8: 9a 81 ldd r25, Y+2 ; 0x02
3fa: 01 96 adiw r24, 0x01 ; 1
3fc: 9a 83 std Y+2, r25 ; 0x02
3fe: 89 83 std Y+1, r24 ; 0x01
400: 89 81 ldd r24, Y+1 ; 0x01
402: 9a 81 ldd r25, Y+2 ; 0x02
404: 01 97 sbiw r24, 0x01 ; 1
406: 61 f4 brne .+24 ; 0x420 <main+0xc4>
crlf();
408: 60 de rcall .-832 ; 0xca <crlf>
io_printString( "Main loop: RI = ");
40a: c4 01 movw r24, r8
40c: 72 de rcall .-796 ; 0xf2 <io_printString>
io_putHex( dataIndex_read );
40e: 80 91 e6 01 lds r24, 0x01E6
412: 80 de rcall .-768 ; 0x114 <io_putHex>
io_printString( " WI = " );
414: c5 01 movw r24, r10
416: 6d de rcall .-806 ; 0xf2 <io_printString>
io_putHex( dataIndex_write );
418: 80 91 e9 01 lds r24, 0x01E9
41c: 7b de rcall .-778 ; 0x114 <io_putHex>
crlf();
41e: 55 de rcall .-854 ; 0xca <crlf>
}
#endif
/* process characters in the buffer */
if( dataIndex_write != dataIndex_read ) {
420: e0 91 e9 01 lds r30, 0x01E9
424: 80 91 e6 01 lds r24, 0x01E6
428: e8 17 cp r30, r24
42a: 19 f3 breq .-58 ; 0x3f2 <main+0x96>
/* here, we have data from the USART in the buffer */
switch( dataBuffer[dataIndex_write] )
42c: 2e 2f mov r18, r30
42e: 30 e0 ldi r19, 0x00 ; 0
430: f9 01 movw r30, r18
432: ea 59 subi r30, 0x9A ; 154
434: fe 4f sbci r31, 0xFE ; 254
436: e0 81 ld r30, Z
438: e9 31 cpi r30, 0x19 ; 25
43a: 61 f0 breq .+24 ; 0x454 <main+0xf8>
43c: ea 31 cpi r30, 0x1A ; 26
43e: 79 f0 breq .+30 ; 0x45e <main+0x102>
440: e8 31 cpi r30, 0x18 ; 24
442: 39 f5 brne .+78 ; 0x492 <main+0x136>
{
case CTRL_X:
INCREMENT_DATA_INDEX_WRITE;
444: 2f 5f subi r18, 0xFF ; 255
446: 3f 4f sbci r19, 0xFF ; 255
448: 2f 77 andi r18, 0x7F ; 127
44a: 30 70 andi r19, 0x00 ; 0
44c: 20 93 e9 01 sts 0x01E9, r18
dumpDataMemory();
450: 8d de rcall .-742 ; 0x16c <dumpDataMemory>
452: cf cf rjmp .-98 ; 0x3f2 <main+0x96>
break;
case CTRL_Y:
crlf();
454: 3a de rcall .-908 ; 0xca <crlf>
io_puts( "Playback data:");
456: c6 01 movw r24, r12
458: 5a de rcall .-844 ; 0x10e <io_puts>
EEPROM_playback(); /* diplay EEPROM contents */
45a: e7 de rcall .-562 ; 0x22a <EEPROM_playback>
45c: 11 c0 rjmp .+34 ; 0x480 <main+0x124>
INCREMENT_DATA_INDEX_WRITE;
break;
case CTRL_Z:
if ( RECORD_OFF == recordMode )
45e: 80 91 64 01 lds r24, 0x0164
462: 88 23 and r24, r24
464: 41 f4 brne .+16 ; 0x476 <main+0x11a>
{
/* here, recording is disabled, enable recording */
recordMode = RECORD_ON;
466: 81 e0 ldi r24, 0x01 ; 1
468: 80 93 64 01 sts 0x0164, r24
crlf();
46c: 2e de rcall .-932 ; 0xca <crlf>
io_puts( "RecMode : ON" );
46e: c8 01 movw r24, r16
470: 4e de rcall .-868 ; 0x10e <io_puts>
/* initialize the EEPROM */
EEPROM_initializeHeader();
472: 22 de rcall .-956 ; 0xb8 <EEPROM_initializeHeader>
474: 05 c0 rjmp .+10 ; 0x480 <main+0x124>
}
else
{
// here, recording is enabled and we need to disable it */
recordMode = RECORD_OFF;
476: 10 92 64 01 sts 0x0164, r1
crlf();
47a: 27 de rcall .-946 ; 0xca <crlf>
io_puts( "RecMode : OFF" );
47c: c7 01 movw r24, r14
47e: 47 de rcall .-882 ; 0x10e <io_puts>
}
INCREMENT_DATA_INDEX_WRITE;
480: 80 91 e9 01 lds r24, 0x01E9
484: 90 e0 ldi r25, 0x00 ; 0
486: 01 96 adiw r24, 0x01 ; 1
488: 8f 77 andi r24, 0x7F ; 127
48a: 90 70 andi r25, 0x00 ; 0
48c: 80 93 e9 01 sts 0x01E9, r24
490: b0 cf rjmp .-160 ; 0x3f2 <main+0x96>
break;
default:
if ( RECORD_ON == recordMode )
492: 80 91 64 01 lds r24, 0x0164
496: 81 30 cpi r24, 0x01 ; 1
498: 11 f4 brne .+4 ; 0x49e <main+0x142>
{
EEPROM_record();
49a: 8c de rcall .-744 ; 0x1b4 <EEPROM_record>
49c: aa cf rjmp .-172 ; 0x3f2 <main+0x96>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
49e: 5d 9b sbis 0x0b, 5 ; 11
4a0: fe cf rjmp .-4 ; 0x49e <main+0x142>
UDR = c;
4a2: ec b9 out 0x0c, r30 ; 12
EEPROM_record();
}
else
{
io_putchar( dataBuffer[dataIndex_write] );
INCREMENT_DATA_INDEX_WRITE;
4a4: 2f 5f subi r18, 0xFF ; 255
4a6: 3f 4f sbci r19, 0xFF ; 255
4a8: 2f 77 andi r18, 0x7F ; 127
4aa: 30 70 andi r19, 0x00 ; 0
4ac: 20 93 e9 01 sts 0x01E9, r18
4b0: a0 cf rjmp .-192 ; 0x3f2 <main+0x96>
000004b2 <_exit>:
4b2: ff cf rjmp .-2 ; 0x4b2 <_exit>
/*-----------------------------------------------------------------------------
Writing Portable Device Drivers
Filename: main.c
Filetype: C source file
Author: Ray Hurst
Created: Mar 15, 2008
Edited: Apr 03, 2008
Description:
LAB 4
Part 1:
Write a driver to cycle the LEDs from 0 to 7 with a delay beteen cycles.
If LED 7 is lit then the next LED lit will be LED 0.
If the corresponding switch (0 to 7) is closed then reset back to LED 0.
Delay controlled by a timer/counter ISR.
Part2:
Activate the USART with the settings 9600-8-N-1.
Accept input from the USART Receiver and echo each character (except ctlr-z
and ctrl-y)
to the USART transmitter.
A ctrl-z character us used to control storing of data to the EEPROM.
A ctrl-y character is used to playback the contents of the EEPROM.
USART operation is as follows:
Record Character Task
Mode Received
X not Echo character to USART TXC
ctrl-x or
ctrl-z or
ctrl-y
0 ctrl-z Clear EEPROM contents and set Recode Mode to 1.
Record mode = 1 starts recording USART data to EEPROM
1 ctrl-z Set Record Mode to 0. Stops recording USART data to
EEPROM.
X ctrl-y playback EEPROM contents to the USART
X ctrl-x display contents of the data SRAM
STK500 Setup:
PORT A - 8 switches used as input
PORT B - 8 LEDs used as output
if LED6 is solid on - ABORTED
Timer\Counter 1 used as delay generator
USART set to Asych normal 9600-8-N-1.
*/
#include "at_mega_8515.h"
#define DEBUG_ENA_PORTD 0
#define DEBUG_EEPROM 1
#define DEBUG_TIMER 0
#define DEBUG_USART 1
/*---------------------------------------------------------------------------*/
/* Function decalarations */
void crlf (void );
void displayData_formatted( uint16_t index, uint8_t data );
uint8_t bin2AsciiHex( uint8_t byte );
void io_printString( const char *s );
void io_putchar ( char c );
void io_putHex( char c );
void io_puts ( const char *s );
void usart_putchar ( char c );
/*---------------------------------------------------------------------------*/
/* Constants */
#define F_CPU 3686400UL /* CPU frequency (Hz) */
#define DELAY_COUNT 4 /* delay count - 18 msec resolution */
#define FALSE 0
#define TRUE 1
#define BIT7 7
#define BIT6 6
#define BIT5 5
#define BIT4 4
#define BIT3 3
#define BIT2 2
#define BIT1 1
#define BIT0 0
#define MAX_LEDS 8
#define MAX_SWITCHES 8
/* LED definitions */
#define ALL_LEDS_OFF 0xFF
#define LED_0_ON ~_BV(BIT0)
#define LED_2_ON ~_BV(BIT2)
#define LED_4_ON ~_BV(BIT4)
#define LED_6_ON ~_BV(BIT6)
#define LED_7_ON ~_BV(BIT7)
#define ABORTED LED_6_ON /* LED to light up when program aborts */
/* USART definitions */
#define USART_BAUDRATE 9600
#define BAUD_PRESCALE_ASYNCH_NORMAL (((F_CPU / (USART_BAUDRATE * 16UL))) - 1 )
#define USART_RXC_FULL ( 0 != (UCSRA & _BV(RXC)) )
#define USART_TXC_EMPTY ( 0 != (UCSRA & _BV(UDRE)) )
/* ASCII control codes */
#define CTRL_X 0x18 /* used to display data SRAM */
#define CTRL_Y 0x19 /* used to playback stored data */
#define CTRL_Z 0x1A /* used to enable/disable record mode */
/*---------------------------------------------------------------------------*/
/* EEPROM data constants */
#define EEPROM_ADDRESS_SIGNATURE 0
#define EEPROM_DATA_SIGNATURE 0x5A
#define EEPROM_ADDRESS_COUNT 1
#define EEPROM_DATA_COUNT_MAX 254
#define EEPROM_ADDRESS_DATA 2
typedef struct
{
uint8_t signature; /* EEPROM data valid signature */
uint8_t count; /* number of bytes recorded */
} EEPROM_HEADER, *P_EEPROM_HEADER;;
/*---------------------------------------------------------------------------*/
/* Hardware Initialization constants */
#define INIT_TCCR1A 0x00
#define INIT_TCCR1B TC1_CS_DIV_1
#define INIT_DDRA_DIR 0x00 /* port A programmed as input port */
#define INIT_DDRB_DIR 0xFF /* port B programmed as output port */
#if (DEBUG_ENA_PORTD)
#define INIT_DDRD_DIR (_BV(DDD2) | _BV(DDD4) | _BV(DDD6))
#endif
#define INIT_PORTD 0x00
/*----------------------------------------------------------------------------*/
/* Global data */
#define DATA_MEMORY_SIZE 512
#define BUFFER_SIZE 128
uint8_t dataBuffer[BUFFER_SIZE];
uint8_t dataIndex_read;
uint8_t dataIndex_write;
#define INCREMENT_DATA_INDEX_READ dataIndex_read = (dataIndex_read + 1) %
BUFFER_SIZE
#define INCREMENT_DATA_INDEX_WRITE dataIndex_write = (dataIndex_write + 1) %
BUFFER_SIZE
#define RECORD_OFF 0
#define RECORD_ON 1
uint8_t recordMode = RECORD_OFF;
EEPROM_HEADER eePromHeader;
/*---------------------------------------------------------------------------*/
/* Abort routine */
void
weAreDead( void )
{
cli(); /* disable global interrupts */
PORTD = ABORTED; /* set PORTD bit 6 - ABORTED */
while(1); /* loop forever */
}
/*---------------------------------------------------------------------------*/
/* EEPROM read/write routines */
/*
Function : EEPROM_read
Description : read a byte from address in EEPROM
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address register */
EEAR = uiAddress;
cli(); /* disable global interrupts */
/* start the EEPROM read process */
EECR |= _BV(EERE);
/* return the data from the data register */
sei(); /* enable global interrupts */
return EEDR;
}
/*
Function : EEPROM_write
Description : write a byte to address in EEPROM (8.5msec program time)
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address and data registers */
EEAR = uiAddress;
EEDR = ucData;
cli(); /* disable global interrupts */
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
/* write the data to EEPROM */
EECR |= _BV(EEWE);
sei(); /* enable global interrupts */
}
/*
Function : EEPROM_displayHeader
Description : display the EEPROM header
*/
void
EEPROM_displayHeader( P_EEPROM_HEADER pEEpromHeader )
{
crlf();
io_printString( "Signature: 0x" );
io_putHex( eePromHeader.signature );
crlf();
io_printString( "Count: 0x" );
io_putHex( eePromHeader.count );
crlf();
}
/*
Function : EEPROM_verifyHeader
Description : read and validate the EEPROM header
*/
uint8_t
EEPROM_verifyHeader( P_EEPROM_HEADER pEEpromHeader )
{
uint8_t dataValid = FALSE; /* assume the EEPROM data is invalid */
/* read signature bytes */
pEEpromHeader->signature = EEPROM_read( EEPROM_ADDRESS_SIGNATURE );
pEEpromHeader->count = EEPROM_read( EEPROM_ADDRESS_COUNT );
if( EEPROM_DATA_SIGNATURE == pEEpromHeader->signature )
dataValid = TRUE;
return dataValid;
}
/*
Function : EEPROM_initialize
Description : write EEPROM header
*/
void
EEPROM_initializeHeader( void )
{
EEPROM_write( EEPROM_ADDRESS_SIGNATURE, EEPROM_DATA_SIGNATURE );
EEPROM_write( EEPROM_ADDRESS_COUNT, 0 );
}
/*
Function : EEPROM_playback
Description : send each byte in the EEPROM to the USART transmitter
*/
void
EEPROM_playback( void )
{
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
uint8_t i, j, data;
EEPROM_displayHeader( &eePromHeader );
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
{
data = EEPROM_read( EEPROM_ADDRESS_DATA + i );
displayData_formatted( j, data );
j++;
}
crlf();
}
else
{
crlf();
io_puts( "EEPROM invalid!" );
}
}
/*
Function : EEPROM_record
Description : store USART data received into EEPROM
*/
void
EEPROM_record( void )
{
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
EEPROM_displayHeader( &eePromHeader );
while( dataIndex_write != dataIndex_read )
{
if ( EEPROM_DATA_COUNT_MAX == eePromHeader.count )
{
crlf();
io_puts( "EEPROM full!" );
dataIndex_write = dataIndex_read; /* discard remaining
characters */
break;
}
else
{
EEPROM_write( EEPROM_ADDRESS_DATA + eePromHeader.count,
dataBuffer[dataIndex_write] );
eePromHeader.count++;
INCREMENT_DATA_INDEX_WRITE;
}
}
/* update EEPROM data log counter */
EEPROM_write( EEPROM_ADDRESS_COUNT, eePromHeader.count );
}
else
{
crlf();
io_puts( "EEPROM invalid!" );
}
}
/*---------------------------------------------------------------------------*/
/* Utility routines */
/*
Function: crlf
Description:
Output CR, LF characters to standard output
*/
void
crlf (void )
{
io_putchar( '\r' );
io_putchar( '\n' );
}
/*
Function: displayData_formatted
Description:
Display data as ASCII hex, neatly formatted 16 bytes per line
*/
void
displayData_formatted ( uint16_t index, uint8_t data )
{
if ( 0 == (index % 16) )
{
crlf();
io_putHex( index >> 8 );
io_putHex( index );
io_putchar( ':' );
}
io_putchar( ' ' );
io_putHex( data );
}
/*
Function: dumpDataMemory
Description:
Display the data memory (512 bytes)
*/
void
dumpDataMemory( void )
{
uint16_t i;
uint8_t *dataPtr = (uint8_t *)0x60;
crlf();
io_puts( "DM Dump:");
for( i = 0; i < 512; i++ )
displayData_formatted( i, *dataPtr++ );
}
/*
Function: bin2AsciiHex
Description:
This function converts a the lower 4 bits of a binary byte into an
ASCII hex character
*/
uint8_t
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
if( byte > 9 )
byte += 7;
byte += '0';
return byte;
}
/*---------------------------------------------------------------------------*/
/* USART I/O routines */
/*
Function: usart_putchar()
Description:
This function writes a single byte to the USART tranmit data register.
*/
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
}
/*---------------------------------------------------------------------------*/
/* I/O routines */
/*
Function: io_printString()
Description:
Output a string pointed to by s to the standard output device.
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
}
/*
Function: io_putchar()
Description:
Output a single character to the standard output device.
*/
void
io_putchar ( char c )
{
usart_putchar( c );
}
/*
Function: io_puts()
Description:
Output a string pointed to by s followed by a newline to the standard
output device.
The terminating null byte is not written.
*/
void
io_puts ( const char *s )
{
io_printString( s );
crlf();
}
/*
Function: io_putHex()
Description:
Convert a byte value into two ASCII hex characters and output
them to the standard output device.
*/
void
io_putHex( char c )
{
io_putchar( bin2AsciiHex(c >> 4) );
io_putchar( bin2AsciiHex(c) );
}
/*---------------------------------------------------------------------------*/
/* Interrupt Sevice Routines (ISRs) */
/* Timer/Counter 1 Overflow Interrupt handler - 20msec interrupt */
/* Configured as an interruptable ISR */
ISR (TIMER1_OVF_vect, ISR_NOBLOCK)
{
static uint8_t i = 0;
static uint8_t delayCount = DELAY_COUNT;
#if (DEBUG_TIMER)
PORTD = PIND ^ _BV(6); /* toggle PORTD pin 6 */
#endif
if( 0 == --delayCount ) {
delayCount = DELAY_COUNT;
PORTB = ~_BV(i);
i = (i + 1) % 8; /* cycle to the next
LED */
/* is the switch coresponding to the lit LED closed? */
if( 0 == (PINA & _BV(i)) )
i = 0; /* here, the
switch is closed */
}
}
/* USART receiver full interrupt */
ISR(USART_RX_vect)
{
/* store the USART data and exit */
dataBuffer[dataIndex_read] = UDR;
INCREMENT_DATA_INDEX_READ; /* note: no buffer overflow
detection */
}
/*---------------------------------------------------------------------------*/
/* main initialization routine */
void
init_system(void)
{
/* initialize global data */
dataIndex_read = dataIndex_write = 0;
/* initialize hardware */
#if (DEBUG_ENA_PORTD)
PORTD = INIT_PORTD;
DDRD = INIT_DDRD_DIR;
#endif
PORTB = ALL_LEDS_OFF; /* initialize PORTB */
DDRB = INIT_DDRB_DIR; /* set PORTB direction register */
DDRA = INIT_DDRA_DIR; /* set PORTA direction register */
/* initialize timer/counter 1 */
TCCR1A = INIT_TCCR1A;
TCCR1B = INIT_TCCR1B;
TIMSK = _BV (TOIE1);
/* initialize USART */
UBRRL = BAUD_PRESCALE_ASYNCH_NORMAL;
UBRRH = BAUD_PRESCALE_ASYNCH_NORMAL >> 8;
UCSRC = USART_REG_SELECT_UCSRC | \
USART_MODE_SELECT_ASYNCHRONOUS | \
USART_PARITY_MODE_NONE | \
USART_STOP_BITS_1 | \
USART_CHAR_SIZE_BITS_8_OR_9;
UCSRB = _BV(RXCIE) | _BV(RXEN) | _BV(TXEN); /* enable USART transmitter /
receiver */
sei(); /* enable global interrupts */
}
/* main routine */
int
main( void )
{
init_system();
crlf();
io_puts( "USART v0.30" ); /* if we see this, we did OK */
crlf();
io_puts( "Ctrl-x - dump data memory" );
io_puts( "Ctrl-z - start/stop data recording" );
io_puts( "Ctrl-y - playback recorded data" );
/* check if EEPROM is initialized */
if( FALSE == EEPROM_verifyHeader(&eePromHeader) ) {
/* EEPROM not initialized here */
crlf();
io_printString( "EEPROM Init ... " );
EEPROM_initializeHeader();
if( FALSE == EEPROM_verifyHeader(&eePromHeader) )
io_puts( "FAIL" );
else
io_puts( "OK" );
crlf();
}
while(1) {
#if (DEBUG_USART)
volatile uint16_t i = 0;
if( 0 == i++ ) {
crlf();
io_printString( "Main loop: RI = ");
io_putHex( dataIndex_read );
io_printString( " WI = " );
io_putHex( dataIndex_write );
crlf();
}
#endif
/* process characters in the buffer */
if( dataIndex_write != dataIndex_read ) {
/* here, we have data from the USART in the buffer */
switch( dataBuffer[dataIndex_write] )
{
case CTRL_X:
INCREMENT_DATA_INDEX_WRITE;
dumpDataMemory();
break;
case CTRL_Y:
crlf();
io_puts( "Playback data:");
EEPROM_playback(); /* diplay EEPROM contents */
INCREMENT_DATA_INDEX_WRITE;
break;
case CTRL_Z:
if ( RECORD_OFF == recordMode )
{
/* here, recording is disabled, enable recording */
recordMode = RECORD_ON;
crlf();
io_puts( "RecMode : ON" );
/* initialize the EEPROM */
EEPROM_initializeHeader();
}
else
{
// here, recording is enabled and we need to disable it */
recordMode = RECORD_OFF;
crlf();
io_puts( "RecMode : OFF" );
}
INCREMENT_DATA_INDEX_WRITE;
break;
default:
if ( RECORD_ON == recordMode )
{
EEPROM_record();
}
else
{
io_putchar( dataBuffer[dataIndex_write] );
INCREMENT_DATA_INDEX_WRITE;
}
break;
}
}
}
return 0;
}
/* End of file main.c */
/******************************************************************************
Filename: at_mega_8515.h
Filetype: C header file
Author: Ray Hurst
Created: 3/10/2008
Edited: 3/14/2008
Description: C header file for the Atmel AVR ATmega8515 Microcontroller
******************************************************************************/
#ifndef _AVR_ATMEGA8515_H_
#define _AVR_ATMEGA8515_H_ 1
#define _EMBEDDED_CLASS_ 1
#ifdef _EMBEDDED_CLASS_
#define cli() __asm__ __volatile__ ("cli" ::)
#define sei() __asm__ __volatile__ ("sei" ::)
typedef unsigned char uint8_t;
typedef unsigned int uint16_t;
#define _MMIO_BYTE(mem_addr) (*(volatile uint8_t *)(mem_addr)) /* macro
for 8 bit general memory access */
#define _MMIO_WORD(mem_addr) (*(volatile uint16_t *)(mem_addr)) /* macro
for 16 bit general memory access */
#define _SFR_IO8(io_addr) _MMIO_BYTE((io_addr) + 0x20) /* macro
for 8 bit register access */
#define _SFR_IO16(io_addr) _MMIO_WORD((io_addr) + 0x20) /* macro
for 16 bit register access */
#define _BV(bit) (1 << (bit))
#define _VECTOR(N) __vector_ ## N /* macro
for interrupt vectors */
#if __GNUC__ >= 4 && __GNUC_MINOR__ >= 1
# define __INTR_ATTRS used, externally_visible
#else /* GCC < 4.1 */
# define __INTR_ATTRS used
#endif
#define ISR(vector, ...) \
void vector (void) __attribute__ ((signal,__INTR_ATTRS)) __VA_ARGS__; \
void vector (void)
# define ISR_NOBLOCK __attribute__((interrupt))
#else /* !_EMBEDDED_CLASS_ */
/* This file should only be included from <avr/io.h>, never directly. */
#ifndef _AVR_IO_H_
# error "Include <avr/io.h> instead of this file."
#endif
#ifndef _AVR_IOXXX_H_
# define _AVR_IOXXX_H_ "at_mega_8515.h"
#else
# error "Attempt to include more than one <avr/ioXXX.h> file."
#endif
#endif /* _EMBEDDED_CLASS_ */
/*---------------------------------------------------------------------------*/
/* Oscillator Calibration Register */
#define OSCCAL _SFR_IO8(0x04)
/*---------------------------------------------------------------------------*/
/* Analog Comparator Control and Status Register */
#define ACSR _SFR_IO8(0x08)
#define ACD 7 /* Analog Comparator Disable, 1 = disable */
#define ACBG 6 /* Analog Comparator Bandgap Select, 1 =
internal, 0 = external */
#define ACO 5 /* Analog Comparator Output */
#define ACI 4 /* Analog Comparator Interrupt Flag */
#define ACIE 3 /* Analog Comparator Interrupt Enable, 1 =
enable */
#define ACIC 2 /* Analog Comparator Input Capture Enable, 1 =
enable */
#define ACIS1 1 /* Analog Comparator Interrupt Mode Select bit
1 */
#define ACIS0 0 /* Analog Comparator Interrupt Mode Select bit
0 */
#define ACSR_MODE_TOGGLE (0) /* analog comparator
interrupt on output toggle */
#define ACSR_MODE_FE _BV(ACIS1) /* analog comparator
interrupt on output falling edge */
#define ACSR_MODE_RE (_BV(ACIS1) | _BV(ACIS0)) /* analog comparator
interrupt on output rising edge */
/*---------------------------------------------------------------------------*/
/* USART - Universal Synchronous and Acychronous serial Receiver and
Transmitter Registers */
#define UBRRL _SFR_IO8(0x09) /* UART Baud Rate Register (LSB) */
#define UCSRB _SFR_IO8(0x0A) /* USART Control and Status Register B */
#define RXCIE 7 /* RX Complete Interrupt Enable */
#define TXCIE 6 /* TX Complete Interrupt Enable */
#define UDRIE 5 /* Data Register Empty Interrupt Enable */
#define RXEN 4 /* Receiver Enable */
#define TXEN 3 /* Transmitter Enable */
#define UCSZ2 2 /* UCSZ bit 2 - set for 9 bit character */
#define RXB8 1 /* Receive Data Bit 8 */
#define TXB8 0 /* Transmit Data Bit 8 */
#define UCSRA _SFR_IO8(0x0B) /* USART Control and Status Register A */
#define RXC 7 /* Receive Complete */
#define TXC 6 /* Transmit Complete */
#define UDRE 5 /* Data Register Empty */
#define FE 4 /* Frame Error */
#define DOR 3 /* Data OverRun */
#define PE 2 /* Parity Error */
#define U2X 1 /* Double the Transmission Speed */
#define MCPM 0 /* Multi-processor Communication mode */
#define UDR _SFR_IO8(0x0C) /* USART I/O Data Register */
#define UBRRH _SFR_IO8(0x20) /* USART Baud Rate Register HI */
#define UCSRC UBRRH /* USART Control and Status Register C */
/* USART Control and Status Register C */
#define URSEL 7 /* USART Register Select, 0 = select UBRRH, 1 =
select UCSRC regsiter */
#define UMSEL 6 /* USART Mode Select, 0 = asynchronous, 1 =
synchronous */
#define UPM1 5 /* USART Parity Mode bit 1 */
#define UPM0 4 /* USART Parity Mode bit 0 */
#define USBS 3 /* USART Stop Bit Select */
#define UCSZ1 2 /* USART Character Size bit 1 */
#define UCSZ0 1 /* USART Character Size bit 0 */
#define UCPOL 0 /* USART Clock Polarity, 0 for asychronous mode
*/
/* Synchronous Mode
UCPOL Transmitted Data Changed Receive
Data Sampled
0 rising XCK edge falling
XCK edge
1 falling XCK edge rising
XCK edge */
#define USART_REG_SELECT_UBBRH (0)
#define USART_REG_SELECT_UCSRC _BV(URSEL)
#define USART_MODE_SELECT_ASYNCHRONOUS (0)
#define USART_MODE_SELECT_SYNCHRONOUS _BV(UMSEL)
#define USART_PARITY_MODE_NONE (0)
#define USART_PARITY_MODE_EVEN _BV(UPM1)
#define USART_PARITY_MODE_ODD (_BV(UPM1) | _BV(UPM0))
#define USART_STOP_BITS_1 (0)
#define USART_STOP_BITS_2 _BV(USBS)
#define USART_CHAR_SIZE_BITS_5 (0)
#define USART_CHAR_SIZE_BITS_6 _BV(UCSZ0)
#define USART_CHAR_SIZE_BITS_7 _BV(UCSZ1)
#define USART_CHAR_SIZE_BITS_7 _BV(UCSZ1)
#define USART_CHAR_SIZE_BITS_8_OR_9 (_BV(UCSZ1) | _BV(UCSZ0)) /* 9 bit
character - must set CHR9 in UCR register */
/*---------------------------------------------------------------------------*/
/* Serial Peripheral Interface (SPI) Registers */
#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */
#define SPIE 7 /* SPI Interrupt Enable, 1 = enable */
#define SPE 6 /* SPI Enable, 1 = enable */
#define DORD 5 /* SPI Data Order, 1 = MSbit first, 0 = LSBit first
*/
#define MSTR 4 /* SPI Master/Slave Select, 1 = master, 0 = slave */
#define CPOL 3 /* SPI Clock Polarity */
/* 1 = SCK high when idle, 0 = SCK low when idle
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising */
#define CPHA 2 /* SPI Clock Phase */
/* CPHA Leading Edge Trailing Edge
0 Sample Setup
1 Setup Sample */
#define SPR1 1 /* SPI Clock Rate Select bit 1 */
#define SPR0 0 /* SPI Clock Rate Select bit 0 */
/* SCK frequency select */
/* Following defines for SPSR register - SPI2X bit must be 0 */
#define SPCR_SPR_DIV_4 (0) /* Fosc divided by
4 */
#define SPCR_SPR_DIV_16 _BV(SPR0) /* Fosc divided by
16 */
#define SPCR_SPR_DIV_64 _BV(SPR1) /* Fosc divided by
64 */
#define SPCR_SPR_DIV_128 (_BV(SPR1) | _BV(SPR0)) /* Fosc divided by
64 */
/* Following defines for SPSR register - SPI2X bit must be 1 */
#define SPCR_SPR_DIV_2 (0) /* Fosc divided by
2 */
#define SPCR_SPR_DIV_8 _BV(SPR0) /* Fosc divided by
8 */
#define SPCR_SPR_DIV_32 _BV(SPR1) /* Fosc divided by
32 */
#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */
#define SPIF 7 /* SPI Interrupt Flag */
#define WCOL 6 /* Write Collision Flag, 1 = collision
occured */
#define SPI2X 0 /* Double SPI Speed, 1 = double SCK frequency
*/
#define SPDR _SFR_IO8(0x0F) /* SPI I/O Data Register */
/*---------------------------------------------------------------------------*/
/* PORT A - E Registers */
/* PORT E register */
#define PINE _SFR_IO8(0x05) /* Input Pins, Port E */
#define DDRE _SFR_IO8(0x06) /* Data Direction Register, Port E */
#define PORTE _SFR_IO8(0x07) /* Data Register, Port E */
#define PE2 2 /* Data Register, Port E pin 2 */
#define PE1 1 /* Data Register, Port E pin 1 */
#define PE0 0 /* Data Register, Port E pin 0 */
#define DDE2 2 /* Data Direction Register, Port E pin 2, 0 =
input, 1 = output */
#define DDE1 1 /* Data Direction Register, Port E pin 1, 0 =
input, 1 = output */
#define DDE0 0 /* Data Direction Register, Port E pin 0, 0 =
input, 1 = output */
/* PORT D register */
#define PIND _SFR_IO8(0x10) /* Input Pins, Port D */
#define DDRD _SFR_IO8(0x11) /* Data Direction Register, Port D */
#define PORTD _SFR_IO8(0x12) /* Data Register, Port D */
#define PD7 7 /* Data Register - Port D bit 7 */
#define PD6 6 /* Data Register - Port D bit 6 */
#define PD5 5 /* Data Register - Port D bit 5 */
#define PD4 4 /* Data Register - Port D bit 4 */
#define PD3 3 /* Data Register - Port D bit 3 */
#define PD2 2 /* Data Register - Port D bit 2 */
#define PD1 1 /* Data Register - Port D bit 1 */
#define PD0 0 /* Data Register - Port D bit 0 */
#define DDD7 7 /* Data Direction Register, Port D bit 7, 0 =
input, 1 = output */
#define DDD6 6 /* Data Direction Register, Port D bit 6, 0 =
input, 1 = output */
#define DDD5 5 /* Data Direction Register, Port D bit 5, 0 =
input, 1 = output */
#define DDD4 4 /* Data Direction Register, Port D bit 4, 0 =
input, 1 = output */
#define DDD3 3 /* Data Direction Register, Port D bit 3, 0 =
input, 1 = output */
#define DDD2 2 /* Data Direction Register, Port D bit 2, 0 =
input, 1 = output */
#define DDD1 1 /* Data Direction Register, Port D bit 1, 0 =
input, 1 = output */
#define DDD0 0 /* Data Direction Register, Port D bit 0, 0 =
input, 1 = output */
/* PORT C register */
#define PINC _SFR_IO8(0x13) /* Input Pins, Port C */
#define DDRC _SFR_IO8(0x14) /* Data Direction Register, Port C */
#define PORTC _SFR_IO8(0x15) /* Data Register, Port C */
#define PC7 7 /* Data Register - Port C bit 7 */
#define PC6 6 /* Data Register - Port C bit 6 */
#define PC5 5 /* Data Register - Port C bit 5 */
#define PC4 4 /* Data Register - Port C bit 4 */
#define PC3 3 /* Data Register - Port C bit 3 */
#define PC2 2 /* Data Register - Port C bit 2 */
#define PC1 1 /* Data Register - Port C bit 1 */
#define PC0 0 /* Data Register - Port C bit 0 */
#define DDC7 7 /* Data Direction Register, Port C bit 7, 0 =
input, 1 = output */
#define DDC6 6 /* Data Direction Register, Port C bit 6, 0 =
input, 1 = output */
#define DDC5 5 /* Data Direction Register, Port C bit 5, 0 =
input, 1 = output */
#define DDC4 4 /* Data Direction Register, Port C bit 4, 0 =
input, 1 = output */
#define DDC3 3 /* Data Direction Register, Port C bit 3, 0 =
input, 1 = output */
#define DDC2 2 /* Data Direction Register, Port C bit 2, 0 =
input, 1 = output */
#define DDC1 1 /* Data Direction Register, Port C bit 1, 0 =
input, 1 = output */
#define DDC0 0 /* Data Direction Register, Port C bit 0, 0 =
input, 1 = output */
/* PORT B register */
#define PINB _SFR_IO8(0x16) /* Input Pins, Port B */
#define DDRB _SFR_IO8(0x17) /* Data Direction Register, Port B */
#define PORTB _SFR_IO8(0x18) /* Data Register, Port B */
#define PB7 7 /* Data Register - Port B bit 7 */
#define PB6 6 /* Data Register - Port B bit 6 */
#define PB5 5 /* Data Register - Port B bit 5 */
#define PB4 4 /* Data Register - Port B bit 4 */
#define PB3 3 /* Data Register - Port B bit 3 */
#define PB2 2 /* Data Register - Port B bit 2 */
#define PB1 1 /* Data Register - Port B bit 1 */
#define PB0 0 /* Data Register - Port B bit 0 */
#define DDB7 7 /* Data Direction Register, Port B bit 7, 0 =
input, 1 = output */
#define DDB6 6 /* Data Direction Register, Port B bit 6, 0 =
input, 1 = output */
#define DDB5 5 /* Data Direction Register, Port B bit 5, 0 =
input, 1 = output */
#define DDB4 4 /* Data Direction Register, Port B bit 4, 0 =
input, 1 = output */
#define DDB3 3 /* Data Direction Register, Port B bit 3, 0 =
input, 1 = output */
#define DDB2 2 /* Data Direction Register, Port B bit 2, 0 =
input, 1 = output */
#define DDB1 1 /* Data Direction Register, Port B bit 1, 0 =
input, 1 = output */
#define DDB0 0 /* Data Direction Register, Port B bit 0, 0 =
input, 1 = output */
/* PORT A register */
#define PINA _SFR_IO8(0x19) /* Input Pins, Port A */
#define DDRA _SFR_IO8(0x1A) /* Data Direction Register, Port A */
#define PORTA _SFR_IO8(0x1B) /* Data Register, Port A */
#define PA7 7 /* Data Register - Port A bit 7 */
#define PA6 6 /* Data Register - Port A bit 6 */
#define PA5 5 /* Data Register - Port A bit 5 */
#define PA4 4 /* Data Register - Port A bit 4 */
#define PA3 3 /* Data Register - Port A bit 3 */
#define PA2 2 /* Data Register - Port A bit 2 */
#define PA1 1 /* Data Register - Port A bit 1 */
#define PA0 0 /* Data Register - Port A bit 0 */
#define DDA7 7 /* Data Direction Register, Port A bit 7, 0 =
input, 1 = output */
#define DDA6 6 /* Data Direction Register, Port A bit 6, 0 =
input, 1 = output */
#define DDA5 5 /* Data Direction Register, Port A bit 5, 0 =
input, 1 = output */
#define DDA4 4 /* Data Direction Register, Port A bit 4, 0 =
input, 1 = output */
#define DDA3 3 /* Data Direction Register, Port A bit 3, 0 =
input, 1 = output */
#define DDA2 2 /* Data Direction Register, Port A bit 2, 0 =
input, 1 = output */
#define DDA1 1 /* Data Direction Register, Port A bit 1, 0 =
input, 1 = output */
#define DDA0 0 /* Data Direction Register, Port A bit 0, 0 =
input, 1 = output */
/*---------------------------------------------------------------------------*/
/* EEPROM Registers */
#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */
#define EERIE 3 /* EEPROM Ready Interrupt Enable, 1 = enable */
#define EEMWE 2 /* EEPROM Master Write Enable, 1 - enable EEWE
bit */
#define EEWE 1 /* EEPROM Write Enable, 1 = write EEPROM */
/* must be done within 4 clocks of writing
EEMWE bit */
#define EERE 0 /* EEPROM Read Enable, 1 = read EEPROM */
#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */
#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register - 16 bit access */
#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register - 8 bit access
(LSB) */
#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register - 8 bit access
(MSB) */
/*---------------------------------------------------------------------------*/
/* Watchdog Register */
#define WDTCR _SFR_IO8(0x21) /* Watchdog Timer Control Register */
#define WDCE 4 /* Watchdog Change Enable */
#define WDE 3 /* Watchdog Enable */
#define WDP2 2 /* Watchdog Timer Prescalar bit 2 */
#define WDP1 1 /* Watchdog Timer Prescalar bit 1 */
#define WDP0 0 /* Watchdog Timer Prescalar bit 0 */
#define WD_CHANGE_ENABLE (_BV(WDCE) | _BV(WDE))
#define WD_TIMER_PRESCALE_16K (0)
#define WD_TIMER_PRESCALE_32K _BV(WDP0)
#define WD_TIMER_PRESCALE_64K _BV(WDP1)
#define WD_TIMER_PRESCALE_128K (_BV(WDP1) | _BV(WDP0))
#define WD_TIMER_PRESCALE_256K _BV(WDP2)
#define WD_TIMER_PRESCALE_512K (_BV(WDP2) | _BV(WDP0))
#define WD_TIMER_PRESCALE_1024K (_BV(WDP2) | _BV(WDP1))
#define WD_TIMER_PRESCALE_2048K (_BV(WDP2) | _BV(WDP1) | _BV(WDP0))
/*---------------------------------------------------------------------------*/
#define SFIOR _SFR_IO8(0x30) /* Special Function IO Register */
#define XMBK 6 /* External Memory Bus Keeper Enable, 1 =
enable */
#define XMM2 5 /* External Memory High Mask - bit 2 */
#define XMM1 4 /* External Memory High Mask - bit 1 */
#define XMM0 3 /* External Memory High Mask - bit 0 */
#define PUD 2 /* Pull-up Disable, 1 = disable */
#define PSR10 0 /* Prescaler Reset Timer/Counter 1 and
Timer/COunter 0, 1 = reset */
/*---------------------------------------------------------------------------*/
/* Timer/Counter 0 & 1 Registers */
#define ICR1 _SFR_IO16(0x24) /* Timer/Counter 1 Input Capture Register - 16
bit access */
#define ICR1L _SFR_IO8(0x24) /* Timer/Counter 1 Input Capture Register - 8
bit access (LSB) */
#define ICR1H _SFR_IO8(0x25) /* Timer/Counter 1 Input Capture Register - 8
bit access (MSB) */
#define OCR1B _SFR_IO16(0x28) /* Timer/Counter1 Output Compare Register B -
16 bit access */
#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter1 Output Compare Register B -
8 bit access (LSB) */
#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter1 Output Compare Register B -
8 bit access (MSB) */
#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter1 Output Compare Register A -
16 bit access */
#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter1 Output Compare Register A -
8 bit access (LSB) */
#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter1 Output Compare Register A -
8 bit access (MSB) */
#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 - 16 bit access */
#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 - 8 bit access (LSB) */
#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 - 8 bit access (MSB) */
#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control and Status Register
*/
#define ICNC1 7 /* Input capture Noise Canceler, 1 = activate */
#define ICES1 6 /* Input capture Edge Select, 0 = falling edge,
1 = positive edge */
#define WGM13 4 /* Waveform Generation Mode bit 3 */
#define WGM12 3 /* Waveform Generation Mode bit 2 */
#define CS12 2 /* Clock Select bit 2 */
#define CS11 1 /* Clock Select bit 1 */
#define CS10 0 /* Clock Select bit 0 */
#define TC1_CS_STOPPED (0) /* timer
stopped */
#define TC1_CS_DIV_1 _BV(CS10) /* prescalar -
divide by 1 */
#define TC1_CS_DIV_8 _BV(CS11) /* prescalar -
divide by 8 */
#define TC1_CS_DIV_64 (_BV(CS11) | _BV(CS10)) /* prescalar -
divide by 64 */
#define TC1_CS_DIV_256 _BV(CS12) /* prescalar -
divide by 256 */
#define TC1_CS_DIV_1024 (_BV(CS12) | _BV(CS10)) /* prescalar -
divide by 1024 */
#define TC1_CS_EXT_FE (_BV(CS12) | _BV(CS11)) /* external
clock on T1 pin, falling edge */
#define TC1_CS_EXT_RE (_BV(CS12) | _BV(CS11) | _BV(CS10)) /* external
clock on T1 pin, rising edge */
#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register */
#define COM1A1 7 /* Compare Ouput Mode for Channel A - bit 1 */
#define COM1A0 6 /* Compare Ouput Mode for Channel A - bit 0 */
#define COM1B1 5 /* Compare Ouput Mode for Channel B - bit 1 */
#define COM1B0 4 /* Compare Ouput Mode for Channel B - bit 0 */
#define FOC1A 3 /* Force Output Compare for Channel A */
#define FOC1B 2 /* Force Output Compare for Channel B */
#define WGM11 1 /* Waveform Generation Mode bit 1 */
#define WGM10 0 /* Waveform Generation Mode bit 0 */
#define OCR0 _SFR_IO8(0x31) /* Timer/Counter 0 Output Compare Register */
#define TCNT0 _SFR_IO8(0x32) /* Timer/Counter 0 */
#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */
#define FOC0 7 /* Force Output Compare, 1 = force */
#define WGM00 6 /* Waveform Generation Mode - bit 0 */
#define COM01 5 /* Compare Match Output Mode - bit 1 */
#define COM00 4 /* Compare Match Output Mode - bit 0 */
#define WGM01 3 /* Waveform Generation Mode - bit 1 */
#define CS02 2 /* Clock Select - bit 2 */
#define CS01 1 /* Clock Select - bit 1 */
#define CS00 0 /* Clock Select - bit 0 */
#define TIFR _SFR_IO8(0x38) /* Timer/Counter Interrupt Flag register */
#define TOV1 7 /* Timer/Counter 1 Overflow Flag, 1 = overflow
*/
#define OCF1A 6 /* Timer/COunter 1 Output Compare A Match Flag,
1 = match */
#define OCF1B 5 /* Timer/COunter 1 Output Compare B Match Flag,
1 = match */
#define ICF1 3 /* Timer/Counter 1 Input Capture Flag, 1 =
input captured */
#define TOV0 1 /* Timer/Counter 0 Overflow Flag, 1 = overflow
*/
#define OCF0 0 /* Output Compare Flag 0, 1 = match */
#define TIMSK _SFR_IO8(0x39) /* Timer/Counter Interrupt MaSK register */
#define TOIE1 7 /* Timer/Counter1 Overflow Interrupt Enable */
#define OCIE1A 6 /* Timer/Counter1 Output Compare A Match
Interrupt Enable */
#define OCIE1B 5 /* Timer/Counter1 Output Compare B Match
Interrupt Enable */
#define TICIE1 3 /* Timer/Counter1 Input Capture Interrupt
Enable */
#define TOIE0 1 /* Timer/Counter0 Overflow Interrupt Enable */
#define OCIE0 0 /* Timer/Counter0 Output Compare Match
Interrupt Enable */
#define TC1_WG_MODE_NORMAL 0 /* count up, cycle 0x0000 to 0xFFFF */
#define TC1_WG_MODE_CTC_OCR1A 4 /* count up, cycle 0x0000 to OCR1A */
#define TC1_SET_WG_MODE
/*---------------------------------------------------------------------------*/
/* MCU Registers */
#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */
#define SM2 5 /* Sleep Mode Select - bit 2 */
#define WDRF 3 /* Watchdog Reset Flag, 1 = watchdog reset
occurred */
#define BORF 2 /* Brown-out Reset Flag, 1 = brown-out reset
occurred */
#define EXTRF 1 /* External Reset Flag, 1 = external reset
occurred */
#define PORF 0 /* Power-on Reset Flag, 1 = power-on reset
occurred */
#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */
#define SRE 7 /* External SRAM/XMEM Enable, 1 = enable */
#define SRW10 6 /* Upper Sector Wait State Select - bit 0 */
#define SE 5 /* Sleep Enable, 1 = enable */
#define SM1 4 /* Sleep Mode Select - bit 1 */
#define ISC11 3 /* Interrupt Sense Control 1 - bit 1 */
#define ISC10 2 /* Interrupt Sense Control 1 - bit 0 */
#define ISC01 1 /* Interrupt Sense Control 0 - bit 1 */
#define ISC00 0 /* Interrupt Sense Control 0 - bit 0 */
#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */
#define SM0 7 /* Sleep Mode Select - bit 0 */
#define SRL2 6 /* Wait State Sector Limit - bit 2 */
#define SRL1 5 /* Wait State Sector Limit - bit 1 */
#define SRL0 4 /* Wait State Sector Limit - bit 0 */
#define SRW01 3 /* Lower Sector Wait State Select - bit 1 */
#define SRW00 2 /* Lower Sector Wait State Select - bit 0 */
#define SRW11 1 /* Upper Sector Wait State Select - bit 1 */
#define ISC2 0 /* Interrupt Sense Control 2 */
#define SLEEP_MODE_IDLE 0
#define SLEEP_MODE_POWER_DOWN 2
#define SLEEP_MODE_STANDBY 6
#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */
#define INTF1 7 /* External Interrupt Flag 1, 1 = INT1 pin
interrupt occurred */
#define INTF0 6 /* External Interrupt Flag 0, 1 = INT0 pin
interrupt occurred */
#define INTF2 5 /* External Interrupt Flag 2, 1 = INT2 pin
interrupt occurred */
#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */
#define INT1 7 /* External Interrupt Request 1 Enable, 1 =
enable INT1 pin */
#define INT0 6 /* External Interrupt Request 0 Enable, 1 =
enable INT0 pin */
#define INT2 5 /* External Interrupt Request 2 Enable, 1 =
enable INT2 pin */
#define IVSEL 1 /* Interrupt Vector Select, 1 = relocate
vectors to FLASH boot loader section */
#define IVCE 0 /* Interrupt Vector Change Enable, 1 = enable
IVSEL bit */
/* 0x3D..0x3E SP */
/* 0x3F SREG */
/*---------------------------------------------------------------------------*/
/* FLASH Read/Write Control Registers */
#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */
#define SPMIE 7 /* SPM Interrupt Enable, 1 = enable */
#define RWWSB 6 /* Read While Write Section Busy, 1 = busy */
#define RWWSRE 4 /* Read While Write Section Read Enable, 1 =
enable */
#define BLBSET 3 /* Boot Lock Bit Set, 1 = set boot lock bits */
#define PGWRT 2 /* Page Write, 1 = execute page write */
#define PGERS 1 /* Page Erase, 1 = execute page erase */
#define SPMEN 0 /* Store Program Memory Enable, 1 = enable */
/*---------------------------------------------------------------------------*/
/* Interrupt vectors */
/* External Interrupt Request 0 */
#define INT0_vect _VECTOR(1)
#define SIG_INTERRUPT0 _VECTOR(1)
/* External Interrupt Request 1 */
#define INT1_vect _VECTOR(2)
#define SIG_INTERRUPT1 _VECTOR(2)
/* Timer/Counter1 Capture Event */
#define TIMER1_CAPT_vect _VECTOR(3)
#define SIG_INPUT_CAPTURE1 _VECTOR(3)
/* Timer/Counter1 Compare Match A */
#define TIMER1_COMPA_vect _VECTOR(4)
#define SIG_OUTPUT_COMPARE1A _VECTOR(4)
/* Timer/Counter1 Compare MatchB */
#define TIMER1_COMPB_vect _VECTOR(5)
#define SIG_OUTPUT_COMPARE1B _VECTOR(5)
/* Timer/Counter1 Overflow */
#define TIMER1_OVF_vect _VECTOR(6)
#define SIG_OVERFLOW1 _VECTOR(6)
/* Timer/Counter0 Overflow */
#define TIMER0_OVF_vect _VECTOR(7)
#define SIG_OVERFLOW0 _VECTOR(7)
/* Serial Transfer Complete */
#define SPI_STC_vect _VECTOR(8)
#define SIG_SPI _VECTOR(8)
/* UART, Rx Complete */
#define USART_RX_vect _VECTOR(9)
#define UART_RX_vect _VECTOR(9) /* For compatability only */
#define SIG_UART_RECV _VECTOR(9) /* For compatability only */
/* UART Data Register Empty */
#define USART_UDRE_vect _VECTOR(10)
#define UART_UDRE_vect _VECTOR(10) /* For compatability only */
#define SIG_UART_DATA _VECTOR(10) /* For compatability only */
/* UART, Tx Complete */
#define USART_TX_vect _VECTOR(11)
#define UART_TX_vect _VECTOR(11) /* For compatability only */
#define SIG_UART_TRANS _VECTOR(11) /* For compatability only */
/* Analog Comparator */
#define ANA_COMP_vect _VECTOR(12)
#define SIG_COMPARATOR _VECTOR(12)
/* External Interrupt Request 2 */
#define INT2_vect _VECTOR(13)
#define SIG_INTERRUPT2 _VECTOR(13)
/* Timer 0 Compare Match */
#define TIMER0_COMP_vect _VECTOR(14)
#define SIG_OUTPUT_COMPARE0 _VECTOR(14)
/* EEPROM Ready */
#define EE_RDY_vect _VECTOR(15)
#define SIG_EEPROM_READY _VECTOR(15)
/* Store Program Memory Ready */
#define SPM_RDY_vect _VECTOR(16)
#define SIG_SPM_READY _VECTOR(16)
#define _VECTORS_SIZE 34
/*---------------------------------------------------------------------------*/
/* Constants */
#define SPM_PAGESIZE 64
#define RAMEND 0x25F /* Last On-Chip SRAM Location */
#define XRAMEND 0xFFFF
#define E2END 0x1FF
#define FLASHEND 0x1FFF
/*---------------------------------------------------------------------------*/
/* Fuses */
#define FUSE_MEMORY_SIZE 2
/* Low Fuse Byte */
#define CKSEL0 ~_BV(0)
#define CKSEL1 ~_BV(1)
#define CKSEL2 ~_BV(2)
#define CKSEL3 ~_BV(3)
#define SUT0 ~_BV(4)
#define SUT1 ~_BV(5)
#define BODEN ~_BV(6)
#define BODLEVEL ~_BV(7)
#define LFUSE_DEFAULT (CKSEL1 & CKSEL2 & CKSEL3 & SUT0)
/* High Fuse Byte */
#define BOOTRST ~_BV(0)
#define BOOTSZ0 ~_BV(1)
#define BOOTSZ1 ~_BV(2)
#define EESAVE ~_BV(3)
#define CKOPT ~_BV(4)
#define SPIEN ~_BV(5)
#define WDTON ~_BV(6)
#define S8515C ~_BV(7)
#define HFUSE_DEFAULT (BOOTSZ0 & BOOTSZ1 & SPIEN)
/* Lock Bits */
#define __LOCK_BITS_EXIST
#define __BOOT_LOCK_BITS_0_EXIST
#define __BOOT_LOCK_BITS_1_EXIST
#endif /* _AVR_ATMEGA8515_H_ */
lab4b.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 00000622 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .data 00000104 00800060 00000622 00000696 2**0
CONTENTS, ALLOC, LOAD, DATA
2 .bss 00000086 00800164 00000726 0000079a 2**0
ALLOC
3 .debug_aranges 00000020 00000000 00000000 0000079a 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_pubnames 000001d6 00000000 00000000 000007ba 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_info 00001033 00000000 00000000 00000990 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_abbrev 000002b4 00000000 00000000 000019c3 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_line 00000aa7 00000000 00000000 00001c77 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_frame 00000160 00000000 00000000 00002720 2**2
CONTENTS, READONLY, DEBUGGING
9 .debug_str 00000253 00000000 00000000 00002880 2**0
CONTENTS, READONLY, DEBUGGING
10 .debug_loc 000001fb 00000000 00000000 00002ad3 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_ranges 00000288 00000000 00000000 00002cce 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 10 c0 rjmp .+32 ; 0x22 <__ctors_end>
2: 2a c0 rjmp .+84 ; 0x58 <__bad_interrupt>
4: 29 c0 rjmp .+82 ; 0x58 <__bad_interrupt>
6: 28 c0 rjmp .+80 ; 0x58 <__bad_interrupt>
8: 27 c0 rjmp .+78 ; 0x58 <__bad_interrupt>
a: 26 c0 rjmp .+76 ; 0x58 <__bad_interrupt>
c: b9 c1 rjmp .+882 ; 0x380 <__vector_6>
e: 24 c0 rjmp .+72 ; 0x58 <__bad_interrupt>
10: 23 c0 rjmp .+70 ; 0x58 <__bad_interrupt>
12: f1 c1 rjmp .+994 ; 0x3f6 <__vector_9>
14: 21 c0 rjmp .+66 ; 0x58 <__bad_interrupt>
16: 20 c0 rjmp .+64 ; 0x58 <__bad_interrupt>
18: 1f c0 rjmp .+62 ; 0x58 <__bad_interrupt>
1a: 1e c0 rjmp .+60 ; 0x58 <__bad_interrupt>
1c: 1d c0 rjmp .+58 ; 0x58 <__bad_interrupt>
1e: 1c c0 rjmp .+56 ; 0x58 <__bad_interrupt>
20: 1b c0 rjmp .+54 ; 0x58 <__bad_interrupt>
00000022 <__ctors_end>:
22: 11 24 eor r1, r1
24: 1f be out 0x3f, r1 ; 63
26: cf e5 ldi r28, 0x5F ; 95
28: d2 e0 ldi r29, 0x02 ; 2
2a: de bf out 0x3e, r29 ; 62
2c: cd bf out 0x3d, r28 ; 61
0000002e <__do_copy_data>:
2e: 11 e0 ldi r17, 0x01 ; 1
30: a0 e6 ldi r26, 0x60 ; 96
32: b0 e0 ldi r27, 0x00 ; 0
34: e2 e2 ldi r30, 0x22 ; 34
36: f6 e0 ldi r31, 0x06 ; 6
38: 02 c0 rjmp .+4 ; 0x3e <.do_copy_data_start>
0000003a <.do_copy_data_loop>:
3a: 05 90 lpm r0, Z+
3c: 0d 92 st X+, r0
0000003e <.do_copy_data_start>:
3e: a4 36 cpi r26, 0x64 ; 100
40: b1 07 cpc r27, r17
42: d9 f7 brne .-10 ; 0x3a <.do_copy_data_loop>
00000044 <__do_clear_bss>:
44: 11 e0 ldi r17, 0x01 ; 1
46: a4 e6 ldi r26, 0x64 ; 100
48: b1 e0 ldi r27, 0x01 ; 1
4a: 01 c0 rjmp .+2 ; 0x4e <.do_clear_bss_start>
0000004c <.do_clear_bss_loop>:
4c: 1d 92 st X+, r1
0000004e <.do_clear_bss_start>:
4e: aa 3e cpi r26, 0xEA ; 234
50: b1 07 cpc r27, r17
52: e1 f7 brne .-8 ; 0x4c <.do_clear_bss_loop>
54: 07 d2 rcall .+1038 ; 0x464 <main>
56: e3 c2 rjmp .+1478 ; 0x61e <_exit>
00000058 <__bad_interrupt>:
58: d3 cf rjmp .-90 ; 0x0 <__vectors>
0000005a <weAreDead>:
/*---------------------------------------------------------------------------*/
/* Abort routine */
void
weAreDead( void )
{
5a: f8 94 cli
cli(); /* disable global interrupts */
PORTD = ABORTED; /* set PORTD bit 6 - ABORTED */
5c: 8f eb ldi r24, 0xBF ; 191
5e: 82 bb out 0x12, r24 ; 18
60: ff cf rjmp .-2 ; 0x60 <weAreDead+0x6>
00000062 <EEPROM_read>:
Function : EEPROM_read
Description : read a byte from address in EEPROM
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
62: e1 99 sbic 0x1c, 1 ; 28
64: fe cf rjmp .-4 ; 0x62 <EEPROM_read>
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address register */
EEAR = uiAddress;
66: 9f bb out 0x1f, r25 ; 31
68: 8e bb out 0x1e, r24 ; 30
cli(); /* disable global interrupts */
6a: f8 94 cli
/* start the EEPROM read process */
EECR |= _BV(EERE);
6c: e0 9a sbi 0x1c, 0 ; 28
/* return the data from the data register */
sei(); /* enable global interrupts */
6e: 78 94 sei
return EEDR;
70: 8d b3 in r24, 0x1d ; 29
}
72: 08 95 ret
00000074 <EEPROM_write>:
Function : EEPROM_write
Description : write a byte to address in EEPROM (8.5msec program time)
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
74: e1 99 sbic 0x1c, 1 ; 28
76: fe cf rjmp .-4 ; 0x74 <EEPROM_write>
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address and data registers */
EEAR = uiAddress;
78: 9f bb out 0x1f, r25 ; 31
7a: 8e bb out 0x1e, r24 ; 30
EEDR = ucData;
7c: 6d bb out 0x1d, r22 ; 29
cli(); /* disable global interrupts */
7e: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
80: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
82: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
84: 78 94 sei
}
86: 08 95 ret
00000088 <EEPROM_verifyHeader>:
Function : EEPROM_verifyHeader
Description : read and validate the EEPROM header
*/
uint8_t
EEPROM_verifyHeader( P_EEPROM_HEADER pEEpromHeader )
{
88: fc 01 movw r30, r24
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
8a: e1 99 sbic 0x1c, 1 ; 28
8c: fe cf rjmp .-4 ; 0x8a <EEPROM_verifyHeader+0x2>
;
/* setup address register */
EEAR = uiAddress;
8e: 1f ba out 0x1f, r1 ; 31
90: 1e ba out 0x1e, r1 ; 30
cli(); /* disable global interrupts */
92: f8 94 cli
/* start the EEPROM read process */
EECR |= _BV(EERE);
94: e0 9a sbi 0x1c, 0 ; 28
/* return the data from the data register */
sei(); /* enable global interrupts */
96: 78 94 sei
return EEDR;
98: 8d b3 in r24, 0x1d ; 29
EEPROM_verifyHeader( P_EEPROM_HEADER pEEpromHeader )
{
uint8_t dataValid = FALSE; /* assume the EEPROM data is invalid */
/* read signature bytes */
pEEpromHeader->signature = EEPROM_read( EEPROM_ADDRESS_SIGNATURE );
9a: 80 83 st Z, r24
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
9c: e1 99 sbic 0x1c, 1 ; 28
9e: fe cf rjmp .-4 ; 0x9c
<EEPROM_verifyHeader+0x14>
;
/* setup address register */
EEAR = uiAddress;
a0: 81 e0 ldi r24, 0x01 ; 1
a2: 90 e0 ldi r25, 0x00 ; 0
a4: 9f bb out 0x1f, r25 ; 31
a6: 8e bb out 0x1e, r24 ; 30
cli(); /* disable global interrupts */
a8: f8 94 cli
/* start the EEPROM read process */
EECR |= _BV(EERE);
aa: e0 9a sbi 0x1c, 0 ; 28
/* return the data from the data register */
sei(); /* enable global interrupts */
ac: 78 94 sei
return EEDR;
ae: 8d b3 in r24, 0x1d ; 29
{
uint8_t dataValid = FALSE; /* assume the EEPROM data is invalid */
/* read signature bytes */
pEEpromHeader->signature = EEPROM_read( EEPROM_ADDRESS_SIGNATURE );
pEEpromHeader->count = EEPROM_read( EEPROM_ADDRESS_COUNT );
b0: 81 83 std Z+1, r24 ; 0x01
b2: 90 e0 ldi r25, 0x00 ; 0
b4: 80 81 ld r24, Z
b6: 8a 35 cpi r24, 0x5A ; 90
b8: 09 f4 brne .+2 ; 0xbc
<EEPROM_verifyHeader+0x34>
ba: 91 e0 ldi r25, 0x01 ; 1
if( EEPROM_DATA_SIGNATURE == pEEpromHeader->signature )
dataValid = TRUE;
return dataValid;
}
bc: 89 2f mov r24, r25
be: 08 95 ret
000000c0 <EEPROM_initializeHeader>:
Function : EEPROM_initialize
Description : write EEPROM header
*/
void
EEPROM_initializeHeader( void )
{
c0: e1 99 sbic 0x1c, 1 ; 28
c2: fe cf rjmp .-4 ; 0xc0 <EEPROM_initializeHeader>
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address and data registers */
EEAR = uiAddress;
c4: 1f ba out 0x1f, r1 ; 31
c6: 1e ba out 0x1e, r1 ; 30
EEDR = ucData;
c8: 8a e5 ldi r24, 0x5A ; 90
ca: 8d bb out 0x1d, r24 ; 29
cli(); /* disable global interrupts */
cc: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
ce: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
d0: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
d2: 78 94 sei
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
d4: e1 99 sbic 0x1c, 1 ; 28
d6: fe cf rjmp .-4 ; 0xd4
<EEPROM_initializeHeader+0x14>
;
/* setup address and data registers */
EEAR = uiAddress;
d8: 81 e0 ldi r24, 0x01 ; 1
da: 90 e0 ldi r25, 0x00 ; 0
dc: 9f bb out 0x1f, r25 ; 31
de: 8e bb out 0x1e, r24 ; 30
EEDR = ucData;
e0: 1d ba out 0x1d, r1 ; 29
cli(); /* disable global interrupts */
e2: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
e4: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
e6: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
e8: 78 94 sei
void
EEPROM_initializeHeader( void )
{
EEPROM_write( EEPROM_ADDRESS_SIGNATURE, EEPROM_DATA_SIGNATURE );
EEPROM_write( EEPROM_ADDRESS_COUNT, 0 );
}
ea: 08 95 ret
000000ec <crlf>:
Description:
Output CR, LF characters to standard output
*/
void
crlf (void )
{
ec: 5d 9b sbis 0x0b, 5 ; 11
ee: fe cf rjmp .-4 ; 0xec <crlf>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
f0: 8d e0 ldi r24, 0x0D ; 13
f2: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
f4: 5d 9b sbis 0x0b, 5 ; 11
f6: fe cf rjmp .-4 ; 0xf4 <crlf+0x8>
UDR = c;
f8: 8a e0 ldi r24, 0x0A ; 10
fa: 8c b9 out 0x0c, r24 ; 12
void
crlf (void )
{
io_putchar( '\r' );
io_putchar( '\n' );
}
fc: 08 95 ret
000000fe <bin2AsciiHex>:
Description:
This function converts a the lower 4 bits of a binary byte into an
ASCII hex character
*/
uint8_t
bin2AsciiHex( uint8_t byte )
{
fe: 8f 70 andi r24, 0x0F ; 15
byte = byte & 0x0F;
if( byte > 9 )
100: 8a 30 cpi r24, 0x0A ; 10
102: 08 f0 brcs .+2 ; 0x106 <bin2AsciiHex+0x8>
byte += 7;
104: 89 5f subi r24, 0xF9 ; 249
byte += '0';
return byte;
}
106: 80 5d subi r24, 0xD0 ; 208
108: 08 95 ret
0000010a <usart_putchar>:
This function writes a single byte to the USART tranmit data register.
*/
void
usart_putchar ( char c )
{
10a: 5d 9b sbis 0x0b, 5 ; 11
10c: fe cf rjmp .-4 ; 0x10a <usart_putchar>
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
10e: 8c b9 out 0x0c, r24 ; 12
}
110: 08 95 ret
00000112 <io_printString>:
Output a string pointed to by s to the standard output device.
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
112: fc 01 movw r30, r24
114: 04 c0 rjmp .+8 ; 0x11e <io_printString+0xc>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
116: 5d 9b sbis 0x0b, 5 ; 11
118: fe cf rjmp .-4 ; 0x116 <io_printString+0x4>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
11a: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
11c: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
11e: 80 81 ld r24, Z
120: 88 23 and r24, r24
122: c9 f7 brne .-14 ; 0x116 <io_printString+0x4>
io_putchar( *s++ );
}
124: 08 95 ret
00000126 <io_putchar>:
Output a single character to the standard output device.
*/
void
io_putchar ( char c )
{
126: 5d 9b sbis 0x0b, 5 ; 11
128: fe cf rjmp .-4 ; 0x126 <io_putchar>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
12a: 8c b9 out 0x0c, r24 ; 12
void
io_putchar ( char c )
{
usart_putchar( c );
}
12c: 08 95 ret
0000012e <io_puts>:
Output a string pointed to by s followed by a newline to the standard
output device.
The terminating null byte is not written.
*/
void
io_puts ( const char *s )
{
12e: fc 01 movw r30, r24
130: 04 c0 rjmp .+8 ; 0x13a <io_puts+0xc>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
132: 5d 9b sbis 0x0b, 5 ; 11
134: fe cf rjmp .-4 ; 0x132 <io_puts+0x4>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
136: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
138: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
13a: 80 81 ld r24, Z
13c: 88 23 and r24, r24
13e: c9 f7 brne .-14 ; 0x132 <io_puts+0x4>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
140: 5d 9b sbis 0x0b, 5 ; 11
142: fe cf rjmp .-4 ; 0x140 <io_puts+0x12>
UDR = c;
144: 8d e0 ldi r24, 0x0D ; 13
146: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
148: 5d 9b sbis 0x0b, 5 ; 11
14a: fe cf rjmp .-4 ; 0x148 <io_puts+0x1a>
UDR = c;
14c: 8a e0 ldi r24, 0x0A ; 10
14e: 8c b9 out 0x0c, r24 ; 12
void
io_puts ( const char *s )
{
io_printString( s );
crlf();
}
150: 08 95 ret
00000152 <io_putHex>:
Description:
Convert a byte value into two ASCII hex characters and output
them to the standard output device.
*/
void
io_putHex( char c )
{
152: 98 2f mov r25, r24
154: 92 95 swap r25
156: 9f 70 andi r25, 0x0F ; 15
*/
uint8_t
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
if( byte > 9 )
158: 9a 30 cpi r25, 0x0A ; 10
15a: 08 f0 brcs .+2 ; 0x15e <io_putHex+0xc>
byte += 7;
15c: 99 5f subi r25, 0xF9 ; 249
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
15e: 5d 9b sbis 0x0b, 5 ; 11
160: fe cf rjmp .-4 ; 0x15e <io_putHex+0xc>
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
if( byte > 9 )
byte += 7;
byte += '0';
162: 90 5d subi r25, 0xD0 ; 208
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
164: 9c b9 out 0x0c, r25 ; 12
This function converts a the lower 4 bits of a binary byte into an
ASCII hex character
*/
uint8_t
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
166: 8f 70 andi r24, 0x0F ; 15
if( byte > 9 )
168: 8a 30 cpi r24, 0x0A ; 10
16a: 08 f0 brcs .+2 ; 0x16e <io_putHex+0x1c>
byte += 7;
16c: 89 5f subi r24, 0xF9 ; 249
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
16e: 5d 9b sbis 0x0b, 5 ; 11
170: fe cf rjmp .-4 ; 0x16e <io_putHex+0x1c>
bin2AsciiHex( uint8_t byte )
{
byte = byte & 0x0F;
if( byte > 9 )
byte += 7;
byte += '0';
172: 80 5d subi r24, 0xD0 ; 208
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
174: 8c b9 out 0x0c, r24 ; 12
void
io_putHex( char c )
{
io_putchar( bin2AsciiHex(c >> 4) );
io_putchar( bin2AsciiHex(c) );
}
176: 08 95 ret
00000178 <displayData_formatted>:
Description:
Display data as ASCII hex, neatly formatted 16 bytes per line
*/
void
displayData_formatted ( uint16_t index, uint8_t data )
{
178: 1f 93 push r17
17a: cf 93 push r28
17c: df 93 push r29
17e: ec 01 movw r28, r24
180: 16 2f mov r17, r22
if ( 0 == (index % 16) )
182: 8f 70 andi r24, 0x0F ; 15
184: 90 70 andi r25, 0x00 ; 0
186: 89 2b or r24, r25
188: 81 f4 brne .+32 ; 0x1aa
<displayData_formatted+0x32>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
18a: 5d 9b sbis 0x0b, 5 ; 11
18c: fe cf rjmp .-4 ; 0x18a
<displayData_formatted+0x12>
UDR = c;
18e: 8d e0 ldi r24, 0x0D ; 13
190: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
192: 5d 9b sbis 0x0b, 5 ; 11
194: fe cf rjmp .-4 ; 0x192
<displayData_formatted+0x1a>
UDR = c;
196: 8a e0 ldi r24, 0x0A ; 10
198: 8c b9 out 0x0c, r24 ; 12
displayData_formatted ( uint16_t index, uint8_t data )
{
if ( 0 == (index % 16) )
{
crlf();
io_putHex( index >> 8 );
19a: 8d 2f mov r24, r29
19c: da df rcall .-76 ; 0x152 <io_putHex>
io_putHex( index );
19e: 8c 2f mov r24, r28
1a0: d8 df rcall .-80 ; 0x152 <io_putHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
1a2: 5d 9b sbis 0x0b, 5 ; 11
1a4: fe cf rjmp .-4 ; 0x1a2
<displayData_formatted+0x2a>
UDR = c;
1a6: 8a e3 ldi r24, 0x3A ; 58
1a8: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
1aa: 5d 9b sbis 0x0b, 5 ; 11
1ac: fe cf rjmp .-4 ; 0x1aa
<displayData_formatted+0x32>
UDR = c;
1ae: 80 e2 ldi r24, 0x20 ; 32
1b0: 8c b9 out 0x0c, r24 ; 12
io_putHex( index >> 8 );
io_putHex( index );
io_putchar( ':' );
}
io_putchar( ' ' );
io_putHex( data );
1b2: 81 2f mov r24, r17
1b4: ce df rcall .-100 ; 0x152 <io_putHex>
}
1b6: df 91 pop r29
1b8: cf 91 pop r28
1ba: 1f 91 pop r17
1bc: 08 95 ret
000001be <dumpDataMemory>:
Description:
Display the data memory (512 bytes)
*/
void
dumpDataMemory( void )
{
1be: cf 93 push r28
1c0: df 93 push r29
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
1c2: 5d 9b sbis 0x0b, 5 ; 11
1c4: fe cf rjmp .-4 ; 0x1c2 <dumpDataMemory+0x4>
UDR = c;
1c6: 8d e0 ldi r24, 0x0D ; 13
1c8: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
1ca: 5d 9b sbis 0x0b, 5 ; 11
1cc: fe cf rjmp .-4 ; 0x1ca <dumpDataMemory+0xc>
UDR = c;
1ce: 8a e0 ldi r24, 0x0A ; 10
1d0: 8c b9 out 0x0c, r24 ; 12
uint16_t i;
uint8_t *dataPtr = (uint8_t *)0x60;
crlf();
io_puts( "DM Dump:");
1d2: 80 e6 ldi r24, 0x60 ; 96
1d4: 90 e0 ldi r25, 0x00 ; 0
1d6: ab df rcall .-170 ; 0x12e <io_puts>
1d8: c0 e0 ldi r28, 0x00 ; 0
1da: d0 e0 ldi r29, 0x00 ; 0
for( i = 0; i < 512; i++ )
displayData_formatted( i, *dataPtr++ );
1dc: fe 01 movw r30, r28
1de: e0 5a subi r30, 0xA0 ; 160
1e0: ff 4f sbci r31, 0xFF ; 255
1e2: 60 81 ld r22, Z
1e4: ce 01 movw r24, r28
1e6: c8 df rcall .-112 ; 0x178 <displayData_formatted>
uint8_t *dataPtr = (uint8_t *)0x60;
crlf();
io_puts( "DM Dump:");
for( i = 0; i < 512; i++ )
1e8: 21 96 adiw r28, 0x01 ; 1
1ea: 82 e0 ldi r24, 0x02 ; 2
1ec: c0 30 cpi r28, 0x00 ; 0
1ee: d8 07 cpc r29, r24
1f0: a9 f7 brne .-22 ; 0x1dc <dumpDataMemory+0x1e>
displayData_formatted( i, *dataPtr++ );
}
1f2: df 91 pop r29
1f4: cf 91 pop r28
1f6: 08 95 ret
000001f8 <EEPROM_displayHeader>:
Function : EEPROM_displayHeader
Description : display the EEPROM header
*/
void
EEPROM_displayHeader( P_EEPROM_HEADER pEEpromHeader )
{
1f8: 5d 9b sbis 0x0b, 5 ; 11
1fa: fe cf rjmp .-4 ; 0x1f8 <EEPROM_displayHeader>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
1fc: 8d e0 ldi r24, 0x0D ; 13
1fe: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
200: 5d 9b sbis 0x0b, 5 ; 11
202: fe cf rjmp .-4 ; 0x200
<EEPROM_displayHeader+0x8>
UDR = c;
204: 8a e0 ldi r24, 0x0A ; 10
206: 8c b9 out 0x0c, r24 ; 12
208: e9 e6 ldi r30, 0x69 ; 105
20a: f0 e0 ldi r31, 0x00 ; 0
20c: 04 c0 rjmp .+8 ; 0x216
<EEPROM_displayHeader+0x1e>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
20e: 5d 9b sbis 0x0b, 5 ; 11
210: fe cf rjmp .-4 ; 0x20e
<EEPROM_displayHeader+0x16>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
212: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
214: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
216: 80 81 ld r24, Z
218: 88 23 and r24, r24
21a: c9 f7 brne .-14 ; 0x20e
<EEPROM_displayHeader+0x16>
void
EEPROM_displayHeader( P_EEPROM_HEADER pEEpromHeader )
{
crlf();
io_printString( "Signature: 0x" );
io_putHex( eePromHeader.signature );
21c: 80 91 e7 01 lds r24, 0x01E7
220: 98 df rcall .-208 ; 0x152 <io_putHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
222: 5d 9b sbis 0x0b, 5 ; 11
224: fe cf rjmp .-4 ; 0x222
<EEPROM_displayHeader+0x2a>
UDR = c;
226: 8d e0 ldi r24, 0x0D ; 13
228: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
22a: 5d 9b sbis 0x0b, 5 ; 11
22c: fe cf rjmp .-4 ; 0x22a
<EEPROM_displayHeader+0x32>
UDR = c;
22e: 8a e0 ldi r24, 0x0A ; 10
230: 8c b9 out 0x0c, r24 ; 12
232: e7 e7 ldi r30, 0x77 ; 119
234: f0 e0 ldi r31, 0x00 ; 0
236: 04 c0 rjmp .+8 ; 0x240
<EEPROM_displayHeader+0x48>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
238: 5d 9b sbis 0x0b, 5 ; 11
23a: fe cf rjmp .-4 ; 0x238
<EEPROM_displayHeader+0x40>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
23c: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
23e: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
240: 80 81 ld r24, Z
242: 88 23 and r24, r24
244: c9 f7 brne .-14 ; 0x238
<EEPROM_displayHeader+0x40>
crlf();
io_printString( "Signature: 0x" );
io_putHex( eePromHeader.signature );
crlf();
io_printString( "Count: 0x" );
io_putHex( eePromHeader.count );
246: 80 91 e8 01 lds r24, 0x01E8
24a: 83 df rcall .-250 ; 0x152 <io_putHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
24c: 5d 9b sbis 0x0b, 5 ; 11
24e: fe cf rjmp .-4 ; 0x24c
<EEPROM_displayHeader+0x54>
UDR = c;
250: 8d e0 ldi r24, 0x0D ; 13
252: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
254: 5d 9b sbis 0x0b, 5 ; 11
256: fe cf rjmp .-4 ; 0x254
<EEPROM_displayHeader+0x5c>
UDR = c;
258: 8a e0 ldi r24, 0x0A ; 10
25a: 8c b9 out 0x0c, r24 ; 12
io_putHex( eePromHeader.signature );
crlf();
io_printString( "Count: 0x" );
io_putHex( eePromHeader.count );
crlf();
}
25c: 08 95 ret
0000025e <EEPROM_record>:
Function : EEPROM_record
Description : store USART data received into EEPROM
*/
void
EEPROM_record( void )
{
25e: 87 ee ldi r24, 0xE7 ; 231
260: 91 e0 ldi r25, 0x01 ; 1
262: 12 df rcall .-476 ; 0x88 <EEPROM_verifyHeader>
264: 81 30 cpi r24, 0x01 ; 1
266: 09 f0 breq .+2 ; 0x26a <__stack+0xb>
268: 4b c0 rjmp .+150 ; 0x300 <__stack+0xa1>
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
EEPROM_displayHeader( &eePromHeader );
26a: 87 ee ldi r24, 0xE7 ; 231
26c: 91 e0 ldi r25, 0x01 ; 1
26e: c4 df rcall .-120 ; 0x1f8 <EEPROM_displayHeader>
while( dataIndex_write != dataIndex_read )
270: 50 91 e6 01 lds r21, 0x01E6
274: 40 91 e8 01 lds r20, 0x01E8
278: e0 91 e9 01 lds r30, 0x01E9
27c: 2d c0 rjmp .+90 ; 0x2d8 <__stack+0x79>
{
if ( EEPROM_DATA_COUNT_MAX == eePromHeader.count )
27e: 4e 3f cpi r20, 0xFE ; 254
280: a1 f4 brne .+40 ; 0x2aa <__stack+0x4b>
282: 40 93 e8 01 sts 0x01E8, r20
286: e0 93 e9 01 sts 0x01E9, r30
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
28a: 5d 9b sbis 0x0b, 5 ; 11
28c: fe cf rjmp .-4 ; 0x28a <__stack+0x2b>
UDR = c;
28e: 8d e0 ldi r24, 0x0D ; 13
290: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
292: 5d 9b sbis 0x0b, 5 ; 11
294: fe cf rjmp .-4 ; 0x292 <__stack+0x33>
UDR = c;
296: 8a e0 ldi r24, 0x0A ; 10
298: 8c b9 out 0x0c, r24 ; 12
while( dataIndex_write != dataIndex_read )
{
if ( EEPROM_DATA_COUNT_MAX == eePromHeader.count )
{
crlf();
io_puts( "EEPROM full!" );
29a: 81 e8 ldi r24, 0x81 ; 129
29c: 90 e0 ldi r25, 0x00 ; 0
29e: 47 df rcall .-370 ; 0x12e <io_puts>
dataIndex_write = dataIndex_read; /* discard remaining
characters */
2a0: 80 91 e6 01 lds r24, 0x01E6
2a4: 80 93 e9 01 sts 0x01E9, r24
2a8: 1d c0 rjmp .+58 ; 0x2e4 <__stack+0x85>
break;
}
else
{
EEPROM_write( EEPROM_ADDRESS_DATA + eePromHeader.count,
dataBuffer[dataIndex_write] );
2aa: 2e 2f mov r18, r30
2ac: 30 e0 ldi r19, 0x00 ; 0
2ae: f9 01 movw r30, r18
2b0: ea 59 subi r30, 0x9A ; 154
2b2: fe 4f sbci r31, 0xFE ; 254
2b4: e0 81 ld r30, Z
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
2b6: e1 99 sbic 0x1c, 1 ; 28
2b8: fe cf rjmp .-4 ; 0x2b6 <__stack+0x57>
break;
}
else
{
EEPROM_write( EEPROM_ADDRESS_DATA + eePromHeader.count,
dataBuffer[dataIndex_write] );
2ba: 84 2f mov r24, r20
2bc: 90 e0 ldi r25, 0x00 ; 0
2be: 02 96 adiw r24, 0x02 ; 2
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address and data registers */
EEAR = uiAddress;
2c0: 9f bb out 0x1f, r25 ; 31
2c2: 8e bb out 0x1e, r24 ; 30
EEDR = ucData;
2c4: ed bb out 0x1d, r30 ; 29
cli(); /* disable global interrupts */
2c6: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
2c8: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
2ca: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
2cc: 78 94 sei
else
{
EEPROM_write( EEPROM_ADDRESS_DATA + eePromHeader.count,
dataBuffer[dataIndex_write] );
eePromHeader.count++;
INCREMENT_DATA_INDEX_WRITE;
2ce: 2f 5f subi r18, 0xFF ; 255
2d0: 3f 4f sbci r19, 0xFF ; 255
2d2: e2 2f mov r30, r18
2d4: ef 77 andi r30, 0x7F ; 127
2d6: 4f 5f subi r20, 0xFF ; 255
EEPROM_record( void )
{
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
EEPROM_displayHeader( &eePromHeader );
while( dataIndex_write != dataIndex_read )
2d8: e5 17 cp r30, r21
2da: 89 f6 brne .-94 ; 0x27e <__stack+0x1f>
2dc: 40 93 e8 01 sts 0x01E8, r20
2e0: e0 93 e9 01 sts 0x01E9, r30
eePromHeader.count++;
INCREMENT_DATA_INDEX_WRITE;
}
}
/* update EEPROM data log counter */
EEPROM_write( EEPROM_ADDRESS_COUNT, eePromHeader.count );
2e4: 20 91 e8 01 lds r18, 0x01E8
*/
void
EEPROM_write( uint16_t uiAddress, uint8_t ucData )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
2e8: e1 99 sbic 0x1c, 1 ; 28
2ea: fe cf rjmp .-4 ; 0x2e8 <__stack+0x89>
;
/* setup address and data registers */
EEAR = uiAddress;
2ec: 81 e0 ldi r24, 0x01 ; 1
2ee: 90 e0 ldi r25, 0x00 ; 0
2f0: 9f bb out 0x1f, r25 ; 31
2f2: 8e bb out 0x1e, r24 ; 30
EEDR = ucData;
2f4: 2d bb out 0x1d, r18 ; 29
cli(); /* disable global interrupts */
2f6: f8 94 cli
/* start the EEPROM write process */
EECR |= _BV(EEMWE);
2f8: e2 9a sbi 0x1c, 2 ; 28
/* write the data to EEPROM */
EECR |= _BV(EEWE);
2fa: e1 9a sbi 0x1c, 1 ; 28
sei(); /* enable global interrupts */
2fc: 78 94 sei
2fe: 08 95 ret
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
300: 5d 9b sbis 0x0b, 5 ; 11
302: fe cf rjmp .-4 ; 0x300 <__stack+0xa1>
UDR = c;
304: 8d e0 ldi r24, 0x0D ; 13
306: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
308: 5d 9b sbis 0x0b, 5 ; 11
30a: fe cf rjmp .-4 ; 0x308 <__stack+0xa9>
UDR = c;
30c: 8a e0 ldi r24, 0x0A ; 10
30e: 8c b9 out 0x0c, r24 ; 12
EEPROM_write( EEPROM_ADDRESS_COUNT, eePromHeader.count );
}
else
{
crlf();
io_puts( "EEPROM invalid!" );
310: 8e e8 ldi r24, 0x8E ; 142
312: 90 e0 ldi r25, 0x00 ; 0
314: 0c df rcall .-488 ; 0x12e <io_puts>
316: 08 95 ret
00000318 <EEPROM_playback>:
Function : EEPROM_playback
Description : send each byte in the EEPROM to the USART transmitter
*/
void
EEPROM_playback( void )
{
318: 1f 93 push r17
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
31a: 87 ee ldi r24, 0xE7 ; 231
31c: 91 e0 ldi r25, 0x01 ; 1
31e: b4 de rcall .-664 ; 0x88 <EEPROM_verifyHeader>
320: 81 30 cpi r24, 0x01 ; 1
322: 09 f5 brne .+66 ; 0x366 <EEPROM_playback+0x4e>
uint8_t i, j, data;
EEPROM_displayHeader( &eePromHeader );
324: 87 ee ldi r24, 0xE7 ; 231
326: 91 e0 ldi r25, 0x01 ; 1
328: 67 df rcall .-306 ; 0x1f8 <EEPROM_displayHeader>
32a: 10 e0 ldi r17, 0x00 ; 0
32c: 0f c0 rjmp .+30 ; 0x34c <EEPROM_playback+0x34>
*/
uint8_t
EEPROM_read( uint16_t uiAddress )
{
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
32e: e1 99 sbic 0x1c, 1 ; 28
330: fe cf rjmp .-4 ; 0x32e <EEPROM_playback+0x16>
EEPROM_displayHeader( &eePromHeader );
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
{
data = EEPROM_read( EEPROM_ADDRESS_DATA + i );
332: 81 2f mov r24, r17
334: 90 e0 ldi r25, 0x00 ; 0
336: 02 96 adiw r24, 0x02 ; 2
/* wait for completion from previous write */
while( EECR & _BV(EEWE) )
;
/* setup address register */
EEAR = uiAddress;
338: 9f bb out 0x1f, r25 ; 31
33a: 8e bb out 0x1e, r24 ; 30
cli(); /* disable global interrupts */
33c: f8 94 cli
/* start the EEPROM read process */
EECR |= _BV(EERE);
33e: e0 9a sbi 0x1c, 0 ; 28
/* return the data from the data register */
sei(); /* enable global interrupts */
340: 78 94 sei
return EEDR;
342: 6d b3 in r22, 0x1d ; 29
EEPROM_displayHeader( &eePromHeader );
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
{
data = EEPROM_read( EEPROM_ADDRESS_DATA + i );
displayData_formatted( j, data );
344: 81 2f mov r24, r17
346: 90 e0 ldi r25, 0x00 ; 0
348: 17 df rcall .-466 ; 0x178 <displayData_formatted>
if( TRUE == EEPROM_verifyHeader(&eePromHeader) ) {
uint8_t i, j, data;
EEPROM_displayHeader( &eePromHeader );
for ( i = 0, j= 0; i < eePromHeader.count; i++ )
34a: 1f 5f subi r17, 0xFF ; 255
34c: 80 91 e8 01 lds r24, 0x01E8
350: 18 17 cp r17, r24
352: 68 f3 brcs .-38 ; 0x32e <EEPROM_playback+0x16>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
354: 5d 9b sbis 0x0b, 5 ; 11
356: fe cf rjmp .-4 ; 0x354 <EEPROM_playback+0x3c>
UDR = c;
358: 8d e0 ldi r24, 0x0D ; 13
35a: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
35c: 5d 9b sbis 0x0b, 5 ; 11
35e: fe cf rjmp .-4 ; 0x35c <EEPROM_playback+0x44>
UDR = c;
360: 8a e0 ldi r24, 0x0A ; 10
362: 8c b9 out 0x0c, r24 ; 12
364: 0b c0 rjmp .+22 ; 0x37c <EEPROM_playback+0x64>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
366: 5d 9b sbis 0x0b, 5 ; 11
368: fe cf rjmp .-4 ; 0x366 <EEPROM_playback+0x4e>
UDR = c;
36a: 8d e0 ldi r24, 0x0D ; 13
36c: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
36e: 5d 9b sbis 0x0b, 5 ; 11
370: fe cf rjmp .-4 ; 0x36e <EEPROM_playback+0x56>
UDR = c;
372: 8a e0 ldi r24, 0x0A ; 10
374: 8c b9 out 0x0c, r24 ; 12
crlf();
}
else
{
crlf();
io_puts( "EEPROM invalid!" );
376: 8e e8 ldi r24, 0x8E ; 142
378: 90 e0 ldi r25, 0x00 ; 0
37a: d9 de rcall .-590 ; 0x12e <io_puts>
}
}
37c: 1f 91 pop r17
37e: 08 95 ret
00000380 <__vector_6>:
/* Interrupt Sevice Routines (ISRs) */
/* Timer/Counter 1 Overflow Interrupt handler - 20msec interrupt */
/* Configured as an interruptable ISR */
ISR (TIMER1_OVF_vect, ISR_NOBLOCK)
{
380: 78 94 sei
382: 1f 92 push r1
384: 0f 92 push r0
386: 0f b6 in r0, 0x3f ; 63
388: 0f 92 push r0
38a: 11 24 eor r1, r1
38c: 2f 93 push r18
38e: 3f 93 push r19
390: 8f 93 push r24
392: 9f 93 push r25
#if (DEBUG_TIMER)
PORTD = PIND ^ _BV(6); /* toggle PORTD pin 6 */
#endif
if( 0 == --delayCount ) {
394: 80 91 63 01 lds r24, 0x0163
398: 81 50 subi r24, 0x01 ; 1
39a: 80 93 63 01 sts 0x0163, r24
39e: 88 23 and r24, r24
3a0: 09 f5 brne .+66 ; 0x3e4 <__vector_6+0x64>
delayCount = DELAY_COUNT;
3a2: 84 e0 ldi r24, 0x04 ; 4
3a4: 80 93 63 01 sts 0x0163, r24
PORTB = ~_BV(i);
3a8: 20 91 65 01 lds r18, 0x0165
3ac: 30 e0 ldi r19, 0x00 ; 0
3ae: 81 e0 ldi r24, 0x01 ; 1
3b0: 90 e0 ldi r25, 0x00 ; 0
3b2: 02 2e mov r0, r18
3b4: 02 c0 rjmp .+4 ; 0x3ba <__vector_6+0x3a>
3b6: 88 0f add r24, r24
3b8: 99 1f adc r25, r25
3ba: 0a 94 dec r0
3bc: e2 f7 brpl .-8 ; 0x3b6 <__vector_6+0x36>
3be: 80 95 com r24
3c0: 88 bb out 0x18, r24 ; 24
i = (i + 1) % 8; /* cycle to the next
LED */
3c2: 2f 5f subi r18, 0xFF ; 255
3c4: 3f 4f sbci r19, 0xFF ; 255
3c6: 27 70 andi r18, 0x07 ; 7
3c8: 30 70 andi r19, 0x00 ; 0
3ca: 20 93 65 01 sts 0x0165, r18
/* is the switch coresponding to the lit LED closed? */
if( 0 == (PINA & _BV(i)) )
3ce: 89 b3 in r24, 0x19 ; 25
3d0: 90 e0 ldi r25, 0x00 ; 0
3d2: 02 c0 rjmp .+4 ; 0x3d8 <__vector_6+0x58>
3d4: 95 95 asr r25
3d6: 87 95 ror r24
3d8: 2a 95 dec r18
3da: e2 f7 brpl .-8 ; 0x3d4 <__vector_6+0x54>
3dc: 80 fd sbrc r24, 0
3de: 02 c0 rjmp .+4 ; 0x3e4 <__vector_6+0x64>
i = 0; /* here, the
switch is closed */
3e0: 10 92 65 01 sts 0x0165, r1
}
}
3e4: 9f 91 pop r25
3e6: 8f 91 pop r24
3e8: 3f 91 pop r19
3ea: 2f 91 pop r18
3ec: 0f 90 pop r0
3ee: 0f be out 0x3f, r0 ; 63
3f0: 0f 90 pop r0
3f2: 1f 90 pop r1
3f4: 18 95 reti
000003f6 <__vector_9>:
/* USART receiver full interrupt */
ISR(USART_RX_vect)
{
3f6: 1f 92 push r1
3f8: 0f 92 push r0
3fa: 0f b6 in r0, 0x3f ; 63
3fc: 0f 92 push r0
3fe: 11 24 eor r1, r1
400: 2f 93 push r18
402: 8f 93 push r24
404: 9f 93 push r25
406: ef 93 push r30
408: ff 93 push r31
/* store the USART data and exit */
dataBuffer[dataIndex_read] = UDR;
40a: 80 91 e6 01 lds r24, 0x01E6
40e: 90 e0 ldi r25, 0x00 ; 0
410: 2c b1 in r18, 0x0c ; 12
412: fc 01 movw r30, r24
414: ea 59 subi r30, 0x9A ; 154
416: fe 4f sbci r31, 0xFE ; 254
418: 20 83 st Z, r18
INCREMENT_DATA_INDEX_READ; /* note: no buffer overflow
detection */
41a: 01 96 adiw r24, 0x01 ; 1
41c: 8f 77 andi r24, 0x7F ; 127
41e: 90 70 andi r25, 0x00 ; 0
420: 80 93 e6 01 sts 0x01E6, r24
}
424: ff 91 pop r31
426: ef 91 pop r30
428: 9f 91 pop r25
42a: 8f 91 pop r24
42c: 2f 91 pop r18
42e: 0f 90 pop r0
430: 0f be out 0x3f, r0 ; 63
432: 0f 90 pop r0
434: 1f 90 pop r1
436: 18 95 reti
00000438 <init_system>:
/*---------------------------------------------------------------------------*/
/* main initialization routine */
void
init_system(void)
{
438: 10 92 e9 01 sts 0x01E9, r1
43c: 10 92 e6 01 sts 0x01E6, r1
#if (DEBUG_ENA_PORTD)
PORTD = INIT_PORTD;
DDRD = INIT_DDRD_DIR;
#endif
PORTB = ALL_LEDS_OFF; /* initialize PORTB */
440: 8f ef ldi r24, 0xFF ; 255
442: 88 bb out 0x18, r24 ; 24
DDRB = INIT_DDRB_DIR; /* set PORTB direction register */
444: 87 bb out 0x17, r24 ; 23
DDRA = INIT_DDRA_DIR; /* set PORTA direction register */
446: 1a ba out 0x1a, r1 ; 26
/* initialize timer/counter 1 */
TCCR1A = INIT_TCCR1A;
448: 1f bc out 0x2f, r1 ; 47
TCCR1B = INIT_TCCR1B;
44a: 81 e0 ldi r24, 0x01 ; 1
44c: 8e bd out 0x2e, r24 ; 46
TIMSK = _BV (TOIE1);
44e: 80 e8 ldi r24, 0x80 ; 128
450: 89 bf out 0x39, r24 ; 57
/* initialize USART */
UBRRL = BAUD_PRESCALE_ASYNCH_NORMAL;
452: 87 e1 ldi r24, 0x17 ; 23
454: 89 b9 out 0x09, r24 ; 9
UBRRH = BAUD_PRESCALE_ASYNCH_NORMAL >> 8;
456: 10 bc out 0x20, r1 ; 32
UCSRC = USART_REG_SELECT_UCSRC | \
458: 86 e8 ldi r24, 0x86 ; 134
45a: 80 bd out 0x20, r24 ; 32
USART_MODE_SELECT_ASYNCHRONOUS | \
USART_PARITY_MODE_NONE | \
USART_STOP_BITS_1 | \
USART_CHAR_SIZE_BITS_8_OR_9;
UCSRB = _BV(RXCIE) | _BV(RXEN) | _BV(TXEN); /* enable USART transmitter /
receiver */
45c: 88 e9 ldi r24, 0x98 ; 152
45e: 8a b9 out 0x0a, r24 ; 10
sei(); /* enable global interrupts */
460: 78 94 sei
}
462: 08 95 ret
00000464 <main>:
/* main routine */
int
main( void )
{
464: ff 92 push r15
466: 0f 93 push r16
468: 1f 93 push r17
46a: df 93 push r29
46c: cf 93 push r28
46e: 00 d0 rcall .+0 ; 0x470 <main+0xc>
470: cd b7 in r28, 0x3d ; 61
472: de b7 in r29, 0x3e ; 62
init_system();
474: e1 df rcall .-62 ; 0x438 <init_system>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
476: 5d 9b sbis 0x0b, 5 ; 11
478: fe cf rjmp .-4 ; 0x476 <main+0x12>
UDR = c;
47a: 8d e0 ldi r24, 0x0D ; 13
47c: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
47e: 5d 9b sbis 0x0b, 5 ; 11
480: fe cf rjmp .-4 ; 0x47e <main+0x1a>
UDR = c;
482: 8a e0 ldi r24, 0x0A ; 10
484: 8c b9 out 0x0c, r24 ; 12
main( void )
{
init_system();
crlf();
io_puts( "USART v0.30" ); /* if we see this, we did OK */
486: 8e e9 ldi r24, 0x9E ; 158
488: 90 e0 ldi r25, 0x00 ; 0
48a: 51 de rcall .-862 ; 0x12e <io_puts>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
48c: 5d 9b sbis 0x0b, 5 ; 11
48e: fe cf rjmp .-4 ; 0x48c <main+0x28>
UDR = c;
490: 8d e0 ldi r24, 0x0D ; 13
492: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
494: 5d 9b sbis 0x0b, 5 ; 11
496: fe cf rjmp .-4 ; 0x494 <main+0x30>
UDR = c;
498: 8a e0 ldi r24, 0x0A ; 10
49a: 8c b9 out 0x0c, r24 ; 12
init_system();
crlf();
io_puts( "USART v0.30" ); /* if we see this, we did OK */
crlf();
io_puts( "Ctrl-x - dump data memory" );
49c: 8a ea ldi r24, 0xAA ; 170
49e: 90 e0 ldi r25, 0x00 ; 0
4a0: 46 de rcall .-884 ; 0x12e <io_puts>
io_puts( "Ctrl-z - start/stop data recording" );
4a2: 84 ec ldi r24, 0xC4 ; 196
4a4: 90 e0 ldi r25, 0x00 ; 0
4a6: 43 de rcall .-890 ; 0x12e <io_puts>
io_puts( "Ctrl-y - playback recorded data" );
4a8: 87 ee ldi r24, 0xE7 ; 231
4aa: 90 e0 ldi r25, 0x00 ; 0
4ac: 40 de rcall .-896 ; 0x12e <io_puts>
/* check if EEPROM is initialized */
if( FALSE == EEPROM_verifyHeader(&eePromHeader) ) {
4ae: 87 ee ldi r24, 0xE7 ; 231
4b0: 91 e0 ldi r25, 0x01 ; 1
4b2: ea dd rcall .-1068 ; 0x88 <EEPROM_verifyHeader>
4b4: 88 23 and r24, r24
4b6: 31 f5 brne .+76 ; 0x504 <main+0xa0>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
4b8: 5d 9b sbis 0x0b, 5 ; 11
4ba: fe cf rjmp .-4 ; 0x4b8 <main+0x54>
UDR = c;
4bc: 8d e0 ldi r24, 0x0D ; 13
4be: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
4c0: 5d 9b sbis 0x0b, 5 ; 11
4c2: fe cf rjmp .-4 ; 0x4c0 <main+0x5c>
UDR = c;
4c4: 8a e0 ldi r24, 0x0A ; 10
4c6: 8c b9 out 0x0c, r24 ; 12
4c8: e7 e0 ldi r30, 0x07 ; 7
4ca: f1 e0 ldi r31, 0x01 ; 1
4cc: 04 c0 rjmp .+8 ; 0x4d6 <main+0x72>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
4ce: 5d 9b sbis 0x0b, 5 ; 11
4d0: fe cf rjmp .-4 ; 0x4ce <main+0x6a>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
4d2: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
4d4: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
4d6: 80 81 ld r24, Z
4d8: 88 23 and r24, r24
4da: c9 f7 brne .-14 ; 0x4ce <main+0x6a>
/* check if EEPROM is initialized */
if( FALSE == EEPROM_verifyHeader(&eePromHeader) ) {
/* EEPROM not initialized here */
crlf();
io_printString( "EEPROM Init ... " );
EEPROM_initializeHeader();
4dc: f1 dd rcall .-1054 ; 0xc0 <EEPROM_initializeHeader>
if( FALSE == EEPROM_verifyHeader(&eePromHeader) )
4de: 87 ee ldi r24, 0xE7 ; 231
4e0: 91 e0 ldi r25, 0x01 ; 1
4e2: d2 dd rcall .-1116 ; 0x88 <EEPROM_verifyHeader>
4e4: 88 23 and r24, r24
4e6: 19 f4 brne .+6 ; 0x4ee <main+0x8a>
io_puts( "FAIL" );
4e8: 88 e1 ldi r24, 0x18 ; 24
4ea: 91 e0 ldi r25, 0x01 ; 1
4ec: 02 c0 rjmp .+4 ; 0x4f2 <main+0x8e>
else
io_puts( "OK" );
4ee: 8d e1 ldi r24, 0x1D ; 29
4f0: 91 e0 ldi r25, 0x01 ; 1
4f2: 1d de rcall .-966 ; 0x12e <io_puts>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
4f4: 5d 9b sbis 0x0b, 5 ; 11
4f6: fe cf rjmp .-4 ; 0x4f4 <main+0x90>
UDR = c;
4f8: 8d e0 ldi r24, 0x0D ; 13
4fa: 8c b9 out 0x0c, r24 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
4fc: 5d 9b sbis 0x0b, 5 ; 11
4fe: fe cf rjmp .-4 ; 0x4fc <main+0x98>
UDR = c;
500: 8a e0 ldi r24, 0x0A ; 10
502: 8c b9 out 0x0c, r24 ; 12
case CTRL_Z:
if ( RECORD_OFF == recordMode )
{
/* here, recording is disabled, enable recording */
recordMode = RECORD_ON;
504: 0d e0 ldi r16, 0x0D ; 13
506: 1a e0 ldi r17, 0x0A ; 10
508: ff 24 eor r15, r15
50a: f3 94 inc r15
crlf();
}
while(1) {
#if (DEBUG_USART)
volatile uint16_t i = 0;
50c: 1a 82 std Y+2, r1 ; 0x02
50e: 19 82 std Y+1, r1 ; 0x01
if( 0 == i++ ) {
510: 89 81 ldd r24, Y+1 ; 0x01
512: 9a 81 ldd r25, Y+2 ; 0x02
514: 01 96 adiw r24, 0x01 ; 1
516: 9a 83 std Y+2, r25 ; 0x02
518: 89 83 std Y+1, r24 ; 0x01
51a: 01 97 sbiw r24, 0x01 ; 1
51c: 31 f5 brne .+76 ; 0x56a <main+0x106>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
51e: 5d 9b sbis 0x0b, 5 ; 11
520: fe cf rjmp .-4 ; 0x51e <main+0xba>
UDR = c;
522: 0c b9 out 0x0c, r16 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
524: 5d 9b sbis 0x0b, 5 ; 11
526: fe cf rjmp .-4 ; 0x524 <main+0xc0>
UDR = c;
528: 1c b9 out 0x0c, r17 ; 12
52a: e0 e2 ldi r30, 0x20 ; 32
52c: f1 e0 ldi r31, 0x01 ; 1
52e: 04 c0 rjmp .+8 ; 0x538 <main+0xd4>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
530: 5d 9b sbis 0x0b, 5 ; 11
532: fe cf rjmp .-4 ; 0x530 <main+0xcc>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
534: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
536: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
538: 80 81 ld r24, Z
53a: 88 23 and r24, r24
53c: c9 f7 brne .-14 ; 0x530 <main+0xcc>
volatile uint16_t i = 0;
if( 0 == i++ ) {
crlf();
io_printString( "Main loop: RI = ");
io_putHex( dataIndex_read );
53e: 80 91 e6 01 lds r24, 0x01E6
542: 07 de rcall .-1010 ; 0x152 <io_putHex>
544: e1 e3 ldi r30, 0x31 ; 49
546: f1 e0 ldi r31, 0x01 ; 1
548: 04 c0 rjmp .+8 ; 0x552 <main+0xee>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
54a: 5d 9b sbis 0x0b, 5 ; 11
54c: fe cf rjmp .-4 ; 0x54a <main+0xe6>
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
io_putchar( *s++ );
54e: 31 96 adiw r30, 0x01 ; 1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
UDR = c;
550: 8c b9 out 0x0c, r24 ; 12
The terminating null byte is not written.
*/
void
io_printString( const char *s )
{
while( '\0' != *s )
552: 80 81 ld r24, Z
554: 88 23 and r24, r24
556: c9 f7 brne .-14 ; 0x54a <main+0xe6>
if( 0 == i++ ) {
crlf();
io_printString( "Main loop: RI = ");
io_putHex( dataIndex_read );
io_printString( " WI = " );
io_putHex( dataIndex_write );
558: 80 91 e9 01 lds r24, 0x01E9
55c: fa dd rcall .-1036 ; 0x152 <io_putHex>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
55e: 5d 9b sbis 0x0b, 5 ; 11
560: fe cf rjmp .-4 ; 0x55e <main+0xfa>
UDR = c;
562: 0c b9 out 0x0c, r16 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
564: 5d 9b sbis 0x0b, 5 ; 11
566: fe cf rjmp .-4 ; 0x564 <main+0x100>
UDR = c;
568: 1c b9 out 0x0c, r17 ; 12
io_putHex( dataIndex_write );
crlf();
}
#endif
/* process characters in the buffer */
if( dataIndex_write != dataIndex_read ) {
56a: e0 91 e9 01 lds r30, 0x01E9
56e: 80 91 e6 01 lds r24, 0x01E6
572: e8 17 cp r30, r24
574: 59 f2 breq .-106 ; 0x50c <main+0xa8>
/* here, we have data from the USART in the buffer */
switch( dataBuffer[dataIndex_write] )
576: 2e 2f mov r18, r30
578: 30 e0 ldi r19, 0x00 ; 0
57a: f9 01 movw r30, r18
57c: ea 59 subi r30, 0x9A ; 154
57e: fe 4f sbci r31, 0xFE ; 254
580: e0 81 ld r30, Z
582: e9 31 cpi r30, 0x19 ; 25
584: 61 f0 breq .+24 ; 0x59e <main+0x13a>
586: ea 31 cpi r30, 0x1A ; 26
588: a9 f0 breq .+42 ; 0x5b4 <main+0x150>
58a: e8 31 cpi r30, 0x18 ; 24
58c: c1 f5 brne .+112 ; 0x5fe <main+0x19a>
{
case CTRL_X:
INCREMENT_DATA_INDEX_WRITE;
58e: 2f 5f subi r18, 0xFF ; 255
590: 3f 4f sbci r19, 0xFF ; 255
592: 2f 77 andi r18, 0x7F ; 127
594: 30 70 andi r19, 0x00 ; 0
596: 20 93 e9 01 sts 0x01E9, r18
dumpDataMemory();
59a: 11 de rcall .-990 ; 0x1be <dumpDataMemory>
59c: b7 cf rjmp .-146 ; 0x50c <main+0xa8>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
59e: 5d 9b sbis 0x0b, 5 ; 11
5a0: fe cf rjmp .-4 ; 0x59e <main+0x13a>
UDR = c;
5a2: 0c b9 out 0x0c, r16 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
5a4: 5d 9b sbis 0x0b, 5 ; 11
5a6: fe cf rjmp .-4 ; 0x5a4 <main+0x140>
UDR = c;
5a8: 1c b9 out 0x0c, r17 ; 12
dumpDataMemory();
break;
case CTRL_Y:
crlf();
io_puts( "Playback data:");
5aa: 89 e3 ldi r24, 0x39 ; 57
5ac: 91 e0 ldi r25, 0x01 ; 1
5ae: bf dd rcall .-1154 ; 0x12e <io_puts>
EEPROM_playback(); /* diplay EEPROM contents */
5b0: b3 de rcall .-666 ; 0x318 <EEPROM_playback>
5b2: 1c c0 rjmp .+56 ; 0x5ec <main+0x188>
INCREMENT_DATA_INDEX_WRITE;
break;
case CTRL_Z:
if ( RECORD_OFF == recordMode )
5b4: 80 91 64 01 lds r24, 0x0164
5b8: 88 23 and r24, r24
5ba: 69 f4 brne .+26 ; 0x5d6 <main+0x172>
{
/* here, recording is disabled, enable recording */
recordMode = RECORD_ON;
5bc: f0 92 64 01 sts 0x0164, r15
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
5c0: 5d 9b sbis 0x0b, 5 ; 11
5c2: fe cf rjmp .-4 ; 0x5c0 <main+0x15c>
UDR = c;
5c4: 0c b9 out 0x0c, r16 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
5c6: 5d 9b sbis 0x0b, 5 ; 11
5c8: fe cf rjmp .-4 ; 0x5c6 <main+0x162>
UDR = c;
5ca: 1c b9 out 0x0c, r17 ; 12
if ( RECORD_OFF == recordMode )
{
/* here, recording is disabled, enable recording */
recordMode = RECORD_ON;
crlf();
io_puts( "RecMode : ON" );
5cc: 88 e4 ldi r24, 0x48 ; 72
5ce: 91 e0 ldi r25, 0x01 ; 1
5d0: ae dd rcall .-1188 ; 0x12e <io_puts>
/* initialize the EEPROM */
EEPROM_initializeHeader();
5d2: 76 dd rcall .-1300 ; 0xc0 <EEPROM_initializeHeader>
5d4: 0b c0 rjmp .+22 ; 0x5ec <main+0x188>
}
else
{
// here, recording is enabled and we need to disable it */
recordMode = RECORD_OFF;
5d6: 10 92 64 01 sts 0x0164, r1
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
5da: 5d 9b sbis 0x0b, 5 ; 11
5dc: fe cf rjmp .-4 ; 0x5da <main+0x176>
UDR = c;
5de: 0c b9 out 0x0c, r16 ; 12
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
5e0: 5d 9b sbis 0x0b, 5 ; 11
5e2: fe cf rjmp .-4 ; 0x5e0 <main+0x17c>
UDR = c;
5e4: 1c b9 out 0x0c, r17 ; 12
else
{
// here, recording is enabled and we need to disable it */
recordMode = RECORD_OFF;
crlf();
io_puts( "RecMode : OFF" );
5e6: 85 e5 ldi r24, 0x55 ; 85
5e8: 91 e0 ldi r25, 0x01 ; 1
5ea: a1 dd rcall .-1214 ; 0x12e <io_puts>
}
INCREMENT_DATA_INDEX_WRITE;
5ec: 80 91 e9 01 lds r24, 0x01E9
5f0: 90 e0 ldi r25, 0x00 ; 0
5f2: 01 96 adiw r24, 0x01 ; 1
5f4: 8f 77 andi r24, 0x7F ; 127
5f6: 90 70 andi r25, 0x00 ; 0
5f8: 80 93 e9 01 sts 0x01E9, r24
5fc: 87 cf rjmp .-242 ; 0x50c <main+0xa8>
break;
default:
if ( RECORD_ON == recordMode )
5fe: 80 91 64 01 lds r24, 0x0164
602: 81 30 cpi r24, 0x01 ; 1
604: 11 f4 brne .+4 ; 0x60a <main+0x1a6>
{
EEPROM_record();
606: 2b de rcall .-938 ; 0x25e <EEPROM_record>
608: 81 cf rjmp .-254 ; 0x50c <main+0xa8>
void
usart_putchar ( char c )
{
/* wait for empty transmit buffer */
while( !( UCSRA & _BV(UDRE)) ) ;
60a: 5d 9b sbis 0x0b, 5 ; 11
60c: fe cf rjmp .-4 ; 0x60a <main+0x1a6>
UDR = c;
60e: ec b9 out 0x0c, r30 ; 12
EEPROM_record();
}
else
{
io_putchar( dataBuffer[dataIndex_write] );
INCREMENT_DATA_INDEX_WRITE;
610: 2f 5f subi r18, 0xFF ; 255
612: 3f 4f sbci r19, 0xFF ; 255
614: 2f 77 andi r18, 0x7F ; 127
616: 30 70 andi r19, 0x00 ; 0
618: 20 93 e9 01 sts 0x01E9, r18
61c: 77 cf rjmp .-274 ; 0x50c <main+0xa8>
0000061e <_exit>:
61e: f8 94 cli
00000620 <__stop_program>:
620: ff cf rjmp .-2 ; 0x620 <__stop_program>
- [avr-gcc-list] Upgraded and re-compiled a current project and a function was converted to in-line and a function.,
Ray Hurst <=