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[avr-gcc-list] Reading of large datatypes from RAM


From: Thilo Schulz
Subject: [avr-gcc-list] Reading of large datatypes from RAM
Date: Thu, 28 Mar 2013 00:05:22 +0100
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Hello,

coming from an x86 C programming background, I've recently found myself 
working alot with atmel's microprocessors and the the avr-gcc toolchain.

I'm writing code for the attiny13 which is severely space-limited, and thus 
have a question/suggestion about how avr-gcc generates code in case of reading 
and writing large data types from/to memory.

Consider this piece of code:

// Global variable curacc: Current accumulated value
uint32_t curacc;

static void check_adc(void)
{
  if((ADCSRA & _BV(ADIF)))
  {
    ADCSRA |= _BV(ADIF);
    
    curacc += ADC;
  }
}

I've found that the compiler translates the line:
    curacc += ADC;

into:
   0x0000025c <fh_timeout+52>:  in      r18, 0x04       ; 4
   0x0000025e <fh_timeout+54>:  in      r19, 0x05       ; 5
   0x00000260 <fh_timeout+56>:  lds     r24, 0x006E
   0x00000264 <fh_timeout+60>:  lds     r25, 0x006F
   0x00000268 <fh_timeout+64>:  lds     r26, 0x0070
   0x0000026c <fh_timeout+68>:  lds     r27, 0x0071
   0x00000270 <fh_timeout+72>:  add     r24, r18
   0x00000272 <fh_timeout+74>:  adc     r25, r19   
   0x00000274 <fh_timeout+76>:  adc     r26, r1
   0x00000276 <fh_timeout+78>:  adc     r27, r1
   0x00000278 <fh_timeout+80>:  sts     0x006E, r24
   0x0000027c <fh_timeout+84>:  sts     0x006F, r25
   0x00000280 <fh_timeout+88>:  sts     0x0070, r26
   0x00000284 <fh_timeout+92>:  sts     0x0071, r27

is there a reason why it has to use 4-byte long direct data space operations?
It might be more beneficial to set up a pointer and use indirect addressing:

in      r18, 0x04       ; 4
in      r19, 0x05       ; 5
clr r31
ldi r30, 0x6E
ld r24, Z+
ld r25, Z+
ld r26, Z+
ld r27, Z
add     r24, r18
adc     r25, r19   
adc     r26, r1
adc     r27, r1
st Z, r27
st -Z, r26
st -Z, r25
st -Z, r24

which would save us 6 words in program space. The benefit would even be greater 
for larger data types.
It comes with a 2-cycle performance penalty though, maybe higher if Z register 
needs to be saved first.

I'm not much into compiler building and have no idea how hard it would be to 
do. I'm just asking out of curiosity.

-- 
Best regards,
Thilo Schulz

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