[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[avr-libc-dev] Iotn13.h
|
From: |
Bruce Graham |
|
Subject: |
[avr-libc-dev] Iotn13.h |
|
Date: |
Thu, 20 May 2004 23:53:55 -0400 |
Ted,
Here is my suggested patch for the header iotn13.h I did not test it
very well since I have been unable to run "avr-as" by itself
successfully. I seem to be short the right document, which I probably
have but can't find, or less likely don't have and can't find.
Some things may be controversial:
(1) When there is no External Memory -- should XRAMEND be 0? or should
it be equal to RAMEND. Actually I could go either way and I can't see
where the symbol is used -- probably in malloc.
(2) Although PB5 is a handy shorthand, the tradition for bit names seems
to be:
(a) use the data sheet name if a name is given
(b) concatenate numbers to the register name if a name is not given
(3) I was not sure what SPEN referred to in register SPMCSR. I could
not find it in the data sheet, nor could I find it in one or two other
data sheets I checked. I hope it was just a mistake, but I could
believe it came form an earlier version of the family.
Bruce
iotn13.log
Description: application/unknown-content-type-txtfile
Index: iotn13/iotn13.h
===================================================================
RCS file: c:\src\master/iotn13/iotn13.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- iotn13/iotn13.h 21 May 2004 00:55:16 -0000 1.1
+++ iotn13/iotn13.h 21 May 2004 03:31:37 -0000 1.2
@@ -23,7 +23,9 @@
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE. */
-/* $Id: iotn13.h,v 1.1 2004/05/21 00:55:16 Bruce Exp $ */
+/* Verified 5/20/04 by Bruce Graham
*/
+
+/* $Id: iotn13.h,v 1.2 2004/05/21 03:31:37 Bruce Exp $ */
/* avr/iotn13.h - definitions for ATtiny13 */
@@ -44,12 +46,14 @@
/* I/O registers and bit names */
+/* ADC Control and Status Register B
*/
#define ADCSRB _SFR_IO8(0x03)
# define ACME 6
# define ADTS2 2
# define ADTS1 1
# define ADTS0 0
+/* ADC Data Register
*/
#ifndef __ASSEMBLER__
#define ADC _SFR_IO16 (0x04)
#endif
@@ -57,6 +61,7 @@
#define ADCL _SFR_IO8(0x04)
#define ADCH _SFR_IO8(0x05)
+/* ADC Control and Status Register A
*/
#define ADCSRA _SFR_IO8(0x06)
# define ADEN 7
# define ADSC 6
@@ -67,12 +72,14 @@
# define ADPS1 1
# define ADPS0 0
+/* ADC Multiplex Selection Register
*/
#define ADMUX _SFR_IO8(0x07)
# define REFS0 6
# define ADLAR 5
# define MUX1 1
# define MUX0 0
+/* Analog Comparator Control and Status Register
*/
#define ACSR _SFR_IO8(0x08)
# define ACD 7
# define ACBG 6
@@ -82,6 +89,7 @@
# define ACIS1 1
# define ACIS0 0
+/* Digital Input Disable Register 0
*/
#define DIDR0 _SFR_IO8(0x14)
# define ADC0D 5
# define ADC2D 4
@@ -90,6 +98,7 @@
# define EIN1D 1
# define AIN0D 0
+/* PIN Change Mask Register
*/
#define PCMSK _SFR_IO8(0x15)
# define PCINT5 5
# define PCINT4 4
@@ -98,6 +107,17 @@
# define PCINT1 1
# define PCINT0 0
+/*
+** Port B Pin Utilization
+** 2535D-AVR-04/04
+** PORTB5 = PCINT5/RESET#/ADC0/dW
+** PORTB4 = PCINT4/ADC2
+** PORTB3 = PCINT3/CLKI/ADC3
+** PORTB2 = SCK/ADC1/T0/PCINT2
+** PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1
+** PORTB0 = MOSI/AIN0/OC0A/PCINT0
+*/
+/* Input Pins, Port B
*/
#define PINB _SFR_IO8(0x16)
# define PINB5 5
# define PINB4 4
@@ -106,6 +126,7 @@
# define PINB1 1
# define PINB0 0
+/* Data Direction Register, Port B
*/
#define DDRB _SFR_IO8(0x17)
# define DDB5 5
# define DDB4 4
@@ -114,18 +135,29 @@
# define DDB1 1
# define DDB0 0
+/* Data Register, Port B
*/
#define PORTB _SFR_IO8(0x18)
-# define PB5 5
-# define PB4 4
-# define PB3 3
-# define PB2 2
-# define PB1 1
-# define PB0 0
-
-/* These are not defined in <avr/io.h> like the rest of the eeprom names. */
+# define PORTB5 5
+# define PORTB4 4
+# define PORTB3 3
+# define PORTB2 2
+# define PORTB1 1
+# define PORTB0 0
+
+/*
+** ATtiny13 has only 64 bytes of EEPROM so EEARH is not required
+** similarly there is no need for word access to EEAR
+*/
+#undef EEAR
+#undef EEARH
+/*
+** EEARL and EECR are defined in io.h, but there are two new bits defined here
+** These are not defined in <avr/io.h> like the other eeprom names.
+*/
# define EEPM1 5
# define EEPM0 4
+/* Watchdog Timer Control Register
*/
#define WDTCR _SFR_IO8(0x21)
# define WDTIF 7
# define WDTIE 6
@@ -136,6 +168,7 @@
# define WDP1 1
# define WDP0 0
+/* Clock Prescale Register
*/
#define CLKPR _SFR_IO8(0x26)
# define CLKPCE 7
# define CLKPS3 3
@@ -143,14 +176,18 @@
# define CLKPS1 1
# define CLKPS0 0
+/* General Timer/Counter Control Register
*/
#define GTCCR _SFR_IO8(0x28)
# define TSM 7
# define PSR10 0
+/* Output Compare 0 Register B
*/
#define OCR0B _SFR_IO8(0x29)
+/* debugWIRE Data Register
*/
#define DWDR _SFR_IO8(0x2e)
+/* Timer/Counter 0 Control Register A
*/
#define TCCR0A _SFR_IO8(0x2f)
# define COM0A1 7
# define COM0A0 6
@@ -159,10 +196,13 @@
# define WGM01 1
# define WGM00 0
+/* Oscillator Calibration Register
*/
#define OSCCAL _SFR_IO8(0x31)
+/* Timer/Counter0 (8-bit)
*/
#define TCNT0 _SFR_IO8(0x32)
+/* Timer/Counter 0 Control Register B
*/
#define TCCR0B _SFR_IO8(0x33)
# define FOC0A 7
# define FOC0B 6
@@ -171,12 +211,14 @@
# define CS01 1
# define CS00 0
+/* MCU General Status Register
*/
#define MCUSR _SFR_IO8(0x34)
# define WDRF 3
# define BORF 2
# define EXTRF 1
# define PORF 0
+/* MCU General Control Register
*/
#define MCUCR _SFR_IO8(0x35)
# define PUD 6
# define SE 5
@@ -185,35 +227,43 @@
# define ISC01 1
# define ISC00 0
+/* Output Compare 0 REgister A
*/
#define OCR0A _SFR_IO8(0x36)
+/* Store Program Memory Control and Status Register
*/
#define SPMCSR _SFR_IO8(0x37)
# define CTPB 4
# define RFLB 3
# define PGWRT 2
# define PGERS 1
-# define SPEN 0
# define SELFPRGEN 0
+/* Timer/Counter 0 Interrupt Flag Register
*/
#define TIFR0 _SFR_IO8(0x38)
# define OCF0B 3
# define OCF0A 2
# define TOV0 1
+/* Timer/Counter 0 Interrupt MaSK Register
*/
#define TIMSK0 _SFR_IO8(0x39)
# define OCIE0B 3
# define OCIE0A 2
# define TOIE0 1
+/* General Interrupt Flag Register
*/
#define GIFR _SFR_IO8(0x3a)
# define INF0 6
# define PCIF 5
+/* General Interrupt MaSK register
*/
#define GIMSK _SFR_IO8(0x3b)
# define INT0 6
# define PCIE 5
-/* SPL and SREG are defined in <avr/io.h> */
+/* SPL and SREG are defined in <avr/io.h> */
+/* SPH is not implemented so undef SPH and SP */
+#undef SP
+#undef SPH
/* From the datasheet:
1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset
@@ -237,11 +287,13 @@
#define SIG_WATCHDOG_TIMEOUT _VECTOR(8)
#define SIG_ADC _VECTOR(9)
-#define _VECTORS_SIZE 20
+#define _MAX_VECTOR_NUMBER 9
+#define _SIZEOF_EACH_VECTOR 2
+#define _VECTORS_SIZE ((_MAX_VECTOR_NUMBER)+1)*_SIZEOF_EACH_VECTOR
#define SPM_PAGESIZE 32
#define RAMEND 0x9F
-#define XRAMEND 0x9F
+#define XRAMEND 0x00
#define E2END 0x3F
#define FLASHEND 0x3FF