[Bug gas/21176] [Aarch64] Wrong syntax accepted for SIMD vector by element operations

[jiwang at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=21176

Jiong Wang <jiwang at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |aarch64*
             Status|UNCONFIRMED                 |ASSIGNED
   Last reconfirmed|                            |2017-02-17
                 CC|                            |jiwang at gcc dot gnu.org
            Version|2.26                        |2.29 (HEAD)
           Assignee|unassigned at sourceware dot org   |jiwang at gcc dot 
gnu.org
     Ever confirmed|0                           |1

--- Comment #1 from Jiong Wang <jiwang at gcc dot gnu.org> ---
(In reply to Ashwin Sekhar T K from comment #0)
> Following syntax is wrong as per Aarch64 specification for vector by element
> operations, but is accepted without any warnings/errors. 
> 
> fmul  v16.4s, v0.4s, v8.4s[0]
> fmla  v20.4s, v0.4s, v8.2s[1]
> fmla  v0.2d, v1.2d, v2.2d[0]
> 
> Correct syntax should be.
> 
> fmul  v16.4s, v0.4s, v8.s[0]
> fmla  v20.4s, v0.4s, v8.s[1]
> fmla  v0.2d, v1.2d, v2.d[0]
> 
> 
> References:
> https://github.com/xianyi/OpenBLAS/commit/
> 278511ad2d1727a7ed74c38e3664b5e51b04adc6
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0802b/
> FMLA_advsimd_elt_vector.html
> 
> Thanks,
> Ashwin

IIRC, aarch64 gcc is using both forms, the assembler is giving some tolerance
on this.  Will confirm whether this is a mistake.

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