[Bug gas/22681] vmovd with qword ptr [rax] is misassembled

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22681

--- Comment #1 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by H.J. Lu <address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=704a705d7aaab8041df76e2981e2a1efc014aad0

commit 704a705d7aaab8041df76e2981e2a1efc014aad0
Author: H.J. Lu <address@hidden>
Date:   Mon Jan 8 04:36:59 2018 -0800

    x86: Properly encode vmovd with 64-bit memeory

    For historical reason, we allow movd/vmovd with 64-bit register and
    memeory operands.  But for vmovd, we failed to handle 64-bit memeory
    operand.  This has been gone unnoticed since AT&T syntax always treats
    memory operand as 32-bit memory.  This patch properly encodes vmovd
    with 64-bit memeory operands.  It also removes AVX512 vmovd with 64-bit
    operands since GCC has

        case TYPE_SSEMOV:
          switch (get_attr_mode (insn))
            {
            case MODE_DI:
              /* Handle broken assemblers that require movd instead of movq. 
*/
              if (!HAVE_AS_IX86_INTERUNIT_MOVQ
                  && (GENERAL_REG_P (operands[0]) || GENERAL_REG_P
(operands[1])))
                return "%vmovd\t{%1, %0|%0, %1}";
              return "%vmovq\t{%1, %0|%0, %1}";

    and all AVX512 GNU assemblers set HAVE_AS_IX86_INTERUNIT_MOVQ, GCC won't
    generate AVX512 vmovd with 64-bit operand.

    gas/

        PR gas/22681
        * testsuite/gas/i386/i386.exp: Run x86-64-movd and
        x86-64-movd-intel.
        * testsuite/gas/i386/x86-64-movd-intel.d: New file.
        * testsuite/gas/i386/x86-64-movd.d: Likewise.
        * testsuite/gas/i386/x86-64-movd.s: Likewise.

    opcodes/

        PR gas/22681
        * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
        Remove AVX512 vmovd with 64-bit operands.
        * i386-tbl.h: Regenerated.

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