[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

[wilson at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22598

--- Comment #4 from Jim Wilson <wilson at gcc dot gnu.org> ---
I would expect this to work
        .option norelax
        beq s1, s0, .+102
        bne a4, a5, .-4096
        jal a2, 1048574
I get
00000000 <.L0 >:
   0:   06848363                beq     s1,s0,66 <.L0 +0x62>
                        0: R_RISCV_BRANCH       .L0 +0x66

00000004 <.L0 >:
   4:   80f71063                bne     a4,a5,fffff004 <.L0 +0xfffff000>
                        4: R_RISCV_BRANCH       .L0 -0x1000
   8:   0000066f                jal     a2,8 <.L0 +0x4>
                        8: R_RISCV_JAL  *ABS*+0xffffe
which looks mostly OK, but the <address> printed doesn't seem to match the
disassembly, or the relocs.  Something (maybe me) appears to be a little
confused here.

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