[Bug gas/22598] [RISCV] No way to disable two-instruction sequences for branch or relocation for jal instructions

[wilson at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22598

--- Comment #6 from Jim Wilson <wilson at gcc dot gnu.org> ---
The address printed for jal is nonsense because it has a reloc, but the address
for the branches should be correct.

I think the problem with the <address> is that we have two ".L0 " fake symbols,
and objdump is using the wrong one.  It just isn't obvious because the symbols
have the same name.  So given
00000000 <.L0 >:
   0:   06848363                beq     s1,s0,66 <.L0 +0x62>
                        0: R_RISCV_BRANCH       .L0 +0x66
00000004 <.L0 >:
The reloc is using the first .L0 because it is embedded in the reloc.  But the
<address> is using the second .L0 because it is closer to the target.  So they
are both correct addresses, they are just confusing because of the symbol
confusion.

The .L0 symbols are assembler fake symbols, that survive into the object file
because they are used by relocs.  Maybe we can teach objdump not to use
assembler fake symbols.

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