[Bug gas/22988] aarch64 sve invalid addressing mode

[cvs-commit at gcc dot gnu.org]

https://sourceware.org/bugzilla/show_bug.cgi?id=22988

--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot 
gnu.org> ---
The master branch has been updated by Nick Clifton <address@hidden>:

https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=c8d59609b1cf66eaff3c486e483f5e3d647c66ff

commit c8d59609b1cf66eaff3c486e483f5e3d647c66ff
Author: Nick Clifton <address@hidden>
Date:   Wed Mar 28 09:44:45 2018 +0100

    Enhance the AARCH64 assembler to support LDFF1xx instructions which use
REG+REG addressing with an assumed offset register.

        PR 22988
    opcode      * opcode/aarch64.h (enum aarch64_opnd): Add
        AARCH64_OPND_SVE_ADDR_R.

    opcodes     * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
        instructions with only a base address register.
        * aarch64-opc.c (operand_general_constraint_met_p): Add code to
        handle AARHC64_OPND_SVE_ADDR_R.
        (aarch64_print_operand): Likewise.
        * aarch64-asm-2.c: Regenerate.
        * aarch64_dis-2.c: Regenerate.
        * aarch64-opc-2.c: Regenerate.

    gas * config/tc-aarch64.c (parse_operands): Add code to handle
        AARCH64_OPN_SVE_ADDR_R.
        * testsuite/gas/aarch64/sve.s: Add tests for LDFF1xx instructions
        with an assumed XZR offset address register.
        * testsuite/gas/aarch64/sve.d: Update expected disassembly.

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