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[Bug binutils/19721] [libopcodes] [Aarch64] Incorrect aliasing for ORR i
From: |
cvs-commit at gcc dot gnu.org |
Subject: |
[Bug binutils/19721] [libopcodes] [Aarch64] Incorrect aliasing for ORR instruction |
Date: |
Mon, 03 Dec 2018 17:35:41 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=19721
--- Comment #3 from cvs-commit at gcc dot gnu.org <cvs-commit at gcc dot
gnu.org> ---
The master branch has been updated by Richard Earnshaw
<address@hidden>:
https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;h=57b64c4103ffeadd524eb80b4a7d61be8c8ec871
commit 57b64c4103ffeadd524eb80b4a7d61be8c8ec871
Author: Egeyar Bagcioglu <address@hidden>
Date: Mon Dec 3 17:31:44 2018 +0000
[aarch64] - Only use MOV for disassembly when shifter op is LSL #0
ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
states that MOV (register) is an alias of the ORR (shifted register)
iff shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov
is currently preferred for a broader range of orr instructions, which
is incorrect.
2018-12-03 Egeyar Bagcioglu <address@hidden>
opcodes:
PR 23193
PR 19721
* aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
encoding as MOV if the shift operation is a left shift of zero.
gas:
PR 23193
PR 19721
* testsuite/gas/aarch64/pr19721.s: Add new test cases.
* testsuite/gas/aarch64/pr19721.d: Correct existing test
cases and add new ones.
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