[Bug binutils/25202] objcopy --verilog-data-width doesn't respect target's endianness

[nickc at redhat dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=25202

--- Comment #15 from Nick Clifton <nickc at redhat dot com> ---
(In reply to Gökçe Aydos from comment #14)

>> I.e. compiling an asm program that starts with .org 0x100, will that cause
>> the address to be set to @40 when using verilog-data-width=4 ?
> 
> Oh, I think that is the actual solution to the word addressing problem
> (compared to my previous comment). Just shift the @addresses n =
> log2(verilog-data-width) to the right, if they have n zeroes in the least
> significant bits. If not, then they should be padded with zeroes.

OK, just to make sure that I understand this correctly...

  * If the start address is 0x100 and the data width is 1 then
    the address in the output file should be "@100".

  * If the start address is 0x111 and the data width is 1 then
    the address in the output file should be "@111".

  * If the start address is 0x100 and the data width is 4 then
    the address in the output file should be "@40".  (ie 0x100 / 4)

  * If the start address is 0x111 and the data width is 4 then
    the address in the output file should be "@44" and the first
    byte should be a padding byte of 00. 

Is that right ?

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