Altivec assembler problems

[Adrian Cox]

The gas in CVS contains support for altivec on powerpc, but has two 
problems:
1) The arguments to vmaddfp are the wrong way round.
2) The altivec cache control instructions are missing.

The attached patch should fix them.

- Adrian Cox, Humboldt Solutions

--- binutils-010113/opcodes/ppc-opc.c   Thu Aug 31 07:48:49 2000
+++ binutils-010113-vec/opcodes/ppc-opc.c       Wed Mar 14 10:20:44 2001
@@ -418,8 +418,13 @@
 #define VD_MASK (0x1f << 21)
   {5, 21, 0, 0, PPC_OPERAND_VR},
 
+ /* The Tag field in a dst ... dssall instruction */
+#define VTAG VD + 1
+#define VTAG_MASK (0x3 << 21)
+  {2, 21, 0, 0, 0},
+
   /* The SIMM field in a VX form instruction. */
-#define SIMM VD + 1
+#define SIMM VTAG + 1
   { 5, 16, 0, 0, PPC_OPERAND_SIGNED},
 
   /* The UIMM field in a VX form instruction. */
@@ -1159,6 +1164,15 @@
 /* An X form instruction.  */
 #define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))
 
+/* An X form data stream instruction */
+#define XDST(op, xop, t) (X((op), (xop)) | (((t) & 1) << 25))
+
+/* The Mask for an X form DST instruction */
+#define XDST_MASK (XDST(0x3f, 0x3ff, 1) | (0x3 << 23))
+
+/* The Mask for a DSS instruction */
+#define XDSS_MASK (XDST_MASK | RA_MASK | RB_MASK)
+
 /* An X form instruction with the RC bit specified.  */
 #define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))
 
@@ -1543,7 +1557,7 @@
 { "vctuxs",    VX(4,  906), VX_MASK,   PPCVEC,         { VD, VB, UIMM } },
 { "vexptefp",  VX(4,  394), VX_MASK,   PPCVEC,         { VD, VB } },
 { "vlogefp",   VX(4,  458), VX_MASK,   PPCVEC,         { VD, VB } },
-{ "vmaddfp",   VXA(4,  46), VXA_MASK,  PPCVEC,         { VD, VA, VB, VC } },
+{ "vmaddfp",   VXA(4,  46), VXA_MASK,  PPCVEC,         { VD, VA, VC, VB } },
 { "vmaxfp",    VX(4, 1034), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 { "vmaxsb",    VX(4,  258), VX_MASK,   PPCVEC,         { VD, VA, VB } },
 { "vmaxsh",    VX(4,  322), VX_MASK,   PPCVEC,         { VD, VA, VB } },
@@ -3212,6 +3226,13 @@
 { "stvewx",  X(31, 199), X_MASK,       PPCVEC,         { VS, RA, RB } },
 { "stvx",    X(31, 231), X_MASK,       PPCVEC,         { VS, RA, RB } },
 { "stvxl",   X(31, 487), X_MASK,       PPCVEC,         { VS, RA, RB } },
+
+{ "dst",     XDST(31, 342, 0), XDST_MASK, PPCVEC,       { RA, RB, VTAG } },
+{ "dstt",    XDST(31, 342, 1), XDST_MASK, PPCVEC,       { RA, RB, VTAG } },
+{ "dstst",   XDST(31, 374, 0), XDST_MASK, PPCVEC,       { RA, RB, VTAG } },
+{ "dststt",  XDST(31, 374, 1), XDST_MASK, PPCVEC,       { RA, RB, VTAG } },
+{ "dss",     XDST(31, 822, 0), XDSS_MASK, PPCVEC,       { VTAG } },
+{ "dssall",  XDST(31, 822, 1), 0xffffffff, PPCVEC,      { 0 } },
 
 { "lwz",     OP(32),   OP_MASK,        PPCCOM,         { RT, D, RA } },
 { "l",      OP(32),    OP_MASK,        PWRCOM,         { RT, D, RA } },