Re: Invalid movzx instruction in GAS-2.11.2

[Alan Modra]

On Mon, Jul 08, 2002 at 12:08:50AM +0200, Gero Kuhlmann wrote:
> .intel_syntax noprefix
> .arch i386
> .code16
> .text
> 
> label1:
>       movzx   eax,word ptr [somevar]
> 
> somevar: .word 0
> ====================================================================
> 
> It should produce '66 0F B7 06 xx xx' with 'xx xx' being the address

Indeed.  Fixed like this:

gas/ChangeLog
        * config/tc-i386.c (process_suffix): Remove intel mode movsx and
        movzx fudges.
        (md_assemble): Instead, zap the suffix here.

include/opcode/ChangeLog
        * i386.h: Remove IgnoreSize from movsx and movzx.

-- 
Alan Modra
IBM OzLabs - Linux Technology Centre

Index: gas/config/tc-i386.c
===================================================================
RCS file: /cvs/src/src/gas/config/tc-i386.c,v
retrieving revision 1.120
diff -u -p -r1.120 tc-i386.c
--- gas/config/tc-i386.c        23 May 2002 13:12:48 -0000      1.120
+++ gas/config/tc-i386.c        8 Jul 2002 09:56:22 -0000
@@ -1326,11 +1326,19 @@ md_assemble (line)
   if (!match_template ())
     return;
 
-  /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
-  if (SYSV386_COMPAT
-      && intel_syntax
-      && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
-    i.tm.base_opcode ^= FloatR;
+  if (intel_syntax)
+    {
+      /* Undo SYSV386_COMPAT brokenness when in Intel mode.  See i386.h  */
+      if (SYSV386_COMPAT
+         && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
+       i.tm.base_opcode ^= FloatR;
+
+      /* Zap movzx and movsx suffix.  The suffix may have been set from
+        "word ptr" or "byte ptr" on the source operand, but we'll use
+        the suffix later to choose the destination register.  */
+      if ((i.tm.base_opcode & ~9) == 0x0fb6)
+       i.suffix = 0;
+    }
 
   if (i.tm.opcode_modifier & FWait)
     if (!add_prefix (FWAIT_OPCODE))
@@ -2218,18 +2226,6 @@ process_suffix ()
       return 0;
     }
 
-  /* For movzx and movsx, need to check the register type.  */
-  if (intel_syntax
-      && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)
-      && i.suffix == BYTE_MNEM_SUFFIX)
-    {
-      unsigned int prefix = DATA_PREFIX_OPCODE;
-
-      if ((i.op[1].regs->reg_type & Reg16) != 0)
-       if (!add_prefix (prefix))
-         return 0;
-    }
-
   if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
     {
       /* It's not a byte, select word/dword operation.  */
Index: include/opcode/i386.h
===================================================================
RCS file: /cvs/src/src/include/opcode/i386.h,v
retrieving revision 1.38
diff -u -p -r1.38 i386.h
--- include/opcode/i386.h       11 Apr 2002 11:58:30 -0000      1.38
+++ include/opcode/i386.h       8 Jul 2002 09:56:27 -0000
@@ -121,9 +121,9 @@ static const template i386_optab[] = {
 {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,            { 
Reg32|WordMem, Reg64, 0} },
 /* Intel Syntax next 5 insns */
 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, 
WordReg, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize,       { 
Reg16|ShortMem, Reg32, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                  { 
Reg16|ShortMem, Reg32, 0} },
 {"movsx",  2, 0x0fbe, X, Cpu64,  b_Suf|Modrm|Rex64,            { Reg8|ByteMem, 
Reg64, 0} },
-{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|IgnoreSize|Rex64, { 
Reg16|ShortMem, Reg64, 0} },
+{"movsx",  2, 0x0fbf, X, Cpu64,  w_Suf|Modrm|Rex64,            { 
Reg16|ShortMem, Reg64, 0} },
 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,            { 
Reg32|WordMem, Reg64, 0} },
 
 /* Move with zero extend.  */
@@ -135,11 +135,11 @@ static const template i386_optab[] = {
 {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,            { 
Reg16|ShortMem, Reg64, 0} },
 /* Intel Syntax next 4 insns */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, 
WordReg, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize,       { 
Reg16|ShortMem, Reg32, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                  { 
Reg16|ShortMem, Reg32, 0} },
 /* These instructions are not particulary usefull, since the zero extend
    32->64 is implicit, but we can encode them.  */
 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64,            { Reg8|ByteMem, 
Reg64, 0} },
-{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { 
Reg16|ShortMem, Reg64, 0} },
+{"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64,            { 
Reg16|ShortMem, Reg64, 0} },
 
 /* Push instructions.  */
 {"push",   1,  0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 
} },