[bug #51338] Support for construction patterns by make functions

[Markus Elfring]

URL:
  <http://savannah.gnu.org/bugs/?51338>

                 Summary: Support for construction patterns by make functions
                 Project: make
            Submitted by: elfring
            Submitted on: Thu 29 Jun 2017 07:55:34 AM CEST
                Severity: 3 - Normal
              Item Group: Enhancement
                  Status: None
                 Privacy: Public
             Assigned to: None
             Open/Closed: Open
         Discussion Lock: Any
       Component Version: 4.2.1
        Operating System: Any
           Fixed Release: None
           Triage Status: None

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Details:

I can construct functions like the following for execution within make
scripts.


my_preparation?=cat
my_compilation?=echo
my_dependencies_1?=a b c
my_dependencies_2?=x y z
my_targets?=Good luck
footer?=Test!

define rule_combination_1 =
${2}.in: ${1}
        $$(my_preparation) "1: $$<" > $$@ 

$(2).txt: $(1) ${2}.in
        $$(my_compilation) "2: $$$$(cat $$< $${footer})" > $$@
endef

$(info $(call rule_combination_1,$(my_dependencies_1),MOTD))

define static_rule_combination_2 =
$(addsuffix .in,$(2)): %.txt: %.in ${1}
        $$(my_preparation) "1: $$<" > $$@

$(addsuffix .msg,$(2)): %.msg: %.txt %.draft ${1}
        $$(my_compilation) "2: $$$$(cat $$< $${footer})" > $$@
endef

$(info $(call static_rule_combination_2,$(my_dependencies_2),${my_targets}))



It seems that such a code example is relatively simple. It tries to express
a general design pattern as make functions:
A data processing step depends on two input files (at least) from which one
of
them (at least again) was automatically generated by a previous process.

I find that there are more software development possibilities to consider.

If I would like to extend this approach in the way that it becomes more
generic
so that the code which will be evaluated in the recipes can be configured
by function call parameters, I guess that I need to use the functionality
“second expansion” then.
It seems that such “secondary expansion
<https://www.gnu.org/software/make/manual/html_node/Secondary-Expansion.html>”
is only directly supported for
prerequisites so far.

Now I imagine that it would be nice if the make software could help a bit
more
in this use case.


There are also some programming languages available which can be executed
from
two file formats.
* Portable code <https://en.wikipedia.org/wiki/Bytecode>
* Machine language <https://en.wikipedia.org/wiki/Machine_code>

Make scripts can support them by a pair of software build rules.

Other data formats (like documentation) are also used where the number of
desired generated end products is even bigger.


So I imagine that there can be a need to move some common functionality into
the make software infrastructure.
How do you think about to support it by extensions for the make function
library
<https://www.gnu.org/software/make/manual/html_node/Extending-make.html>?




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