[Commit-gnuradio] r3522 - usrp-hw/trunk/sym/generated

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[Commit-gnuradio] r3522 - usrp-hw/trunk/sym/generated

From:	matt
Subject:	[Commit-gnuradio] r3522 - usrp-hw/trunk/sym/generated
Date:	Mon, 11 Sep 2006 13:36:23 -0600 (MDT)
Author: matt
Date: 2006-09-11 13:36:23 -0600 (Mon, 11 Sep 2006)
New Revision: 3522

Added:
   usrp-hw/trunk/sym/generated/fg456_table.csv
   usrp-hw/trunk/sym/generated/xilinxgen
Modified:
   usrp-hw/trunk/sym/generated/make_symbols
Log:
xilinx Spartan 3 400/1000/1500/2000 FG456


Added: usrp-hw/trunk/sym/generated/fg456_table.csv
===================================================================
--- usrp-hw/trunk/sym/generated/fg456_table.csv                         (rev 0)
+++ usrp-hw/trunk/sym/generated/fg456_table.csv 2006-09-11 19:36:23 UTC (rev 
3522)
@@ -0,0 +1,457 @@
+SORT_ROW,SORT_ROW_#,SORT_COLUMN,PIN_NUMBER,XC3S400,XC3S400_TYPE,XC3S1000,XC3S1000_TYPE,XC3S1500,XC3S1500_TYPE,XC3S2000,XC3S2000_TYPE,BANK
+A,1,1,A1,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+A,1,2,A2,PROG_B,CONFIG,PROG_B,CONFIG,PROG_B,CONFIG,PROG_B,CONFIG,VCCAUX
+A,1,3,A3,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+A,1,4,A4,IO_L01P_0/VRN_0,DCI,IO_L01P_0/VRN_0,DCI,IO_L01P_0/VRN_0,DCI,IO_L01P_0/VRN_0,DCI,0
+A,1,5,A5,IO_L09P_0,I/O,IO_L09P_0,I/O,IO_L09P_0,I/O,IO_L09P_0,I/O,0
+A,1,6,A6,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+A,1,7,A7,N.C.,N.C.,IO_L19P_0,I/O,IO_L19P_0,I/O,IO_L19P_0,I/O,0
+A,1,8,A8,IO_L24P_0,I/O,IO_L24P_0,I/O,IO_L24P_0,I/O,IO_L24P_0,I/O,0
+A,1,9,A9,IO_L27P_0,I/O,IO_L27P_0,I/O,IO_L27P_0,I/O,IO_L27P_0,I/O,0
+A,1,10,A10,IO,I/O,IO,I/O,IO,I/O,IO,I/O,0
+A,1,11,A11,IO_L32P_0/GCLK6,GCLK,IO_L32P_0/GCLK6,GCLK,IO_L32P_0/GCLK6,GCLK,IO_L32P_0/GCLK6,GCLK,0
+A,1,12,A12,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+A,1,13,A13,IO_L30N_1,I/O,IO_L30N_1,I/O,IO_L30N_1,I/O,IO_L30N_1,I/O,1
+A,1,14,A14,IO_L28N_1,I/O,IO_L28N_1,I/O,IO_L28N_1,I/O,IO_L28N_1,I/O,1
+A,1,15,A15,IO_L25P_1,I/O,IO_L25P_1,I/O,IO_L25P_1,I/O,IO_L25P_1,I/O,1
+A,1,16,A16,N.C.,N.C.,IO_L22N_1,I/O,IO_L22N_1,I/O,IO_L22N_1,I/O,1
+A,1,17,A17,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+A,1,18,A18,IO_L10N_1/VREF_1,VREF,IO_L10N_1/VREF_1,VREF,IO_L10N_1/VREF_1,VREF,IO_L10N_1/VREF_1,VREF,1
+A,1,19,A19,IO_L06N_1/VREF_1,VREF,IO_L06N_1/VREF_1,VREF,IO_L06N_1/VREF_1,VREF,IO_L06N_1/VREF_1,VREF,1
+A,1,20,A20,TMS,JTAG,TMS,JTAG,TMS,JTAG,TMS,JTAG,VCCAUX
+A,1,21,A21,TCK,JTAG,TCK,JTAG,TCK,JTAG,TCK,JTAG,VCCAUX
+A,1,22,A22,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+B,2,1,B1,TDI,JTAG,TDI,JTAG,TDI,JTAG,TDI,JTAG,VCCAUX
+B,2,2,B2,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+B,2,3,B3,HSWAP_EN,CONFIG,HSWAP_EN,CONFIG,HSWAP_EN,CONFIG,HSWAP_EN,CONFIG,VCCAUX
+B,2,4,B4,IO_L01N_0/VRP_0,DCI,IO_L01N_0/VRP_0,DCI,IO_L01N_0/VRP_0,DCI,IO_L01N_0/VRP_0,DCI,0
+B,2,5,B5,IO_L09N_0,I/O,IO_L09N_0,I/O,IO_L09N_0,I/O,IO_L09N_0,I/O,0
+B,2,6,B6,IO_L15P_0,I/O,IO_L15P_0,I/O,IO_L15P_0,I/O,IO_L15P_0,I/O,0
+B,2,7,B7,N.C.,N.C.,IO_L19N_0,I/O,IO_L19N_0,I/O,IO_L19N_0,I/O,0
+B,2,8,B8,IO_L24N_0,I/O,IO_L24N_0,I/O,IO_L24N_0,I/O,IO_L24N_0,I/O,0
+B,2,9,B9,IO_L27N_0,I/O,IO_L27N_0,I/O,IO_L27N_0,I/O,IO_L27N_0,I/O,0
+B,2,10,B10,IO_L29P_0,I/O,IO_L29P_0,I/O,IO_L29P_0,I/O,IO_L29P_0,I/O,0
+B,2,11,B11,IO_L32N_0/GCLK7,GCLK,IO_L32N_0/GCLK7,GCLK,IO_L32N_0/GCLK7,GCLK,IO_L32N_0/GCLK7,GCLK,0
+B,2,12,B12,IO_L32N_1/GCLK5,GCLK,IO_L32N_1/GCLK5,GCLK,IO_L32N_1/GCLK5,GCLK,IO_L32N_1/GCLK5,GCLK,1
+B,2,13,B13,IO_L30P_1,I/O,IO_L30P_1,I/O,IO_L30P_1,I/O,IO_L30P_1,I/O,1
+B,2,14,B14,IO_L28P_1,I/O,IO_L28P_1,I/O,IO_L28P_1,I/O,IO_L28P_1,I/O,1
+B,2,15,B15,IO_L25N_1,I/O,IO_L25N_1,I/O,IO_L25N_1,I/O,IO_L25N_1,I/O,1
+B,2,16,B16,N.C.,N.C.,IO_L22P_1,I/O,IO_L22P_1,I/O,IO_L22P_1,I/O,1
+B,2,17,B17,IO_L16N_1,I/O,IO_L16N_1,I/O,IO_L16N_1,I/O,IO_L16N_1,I/O,1
+B,2,18,B18,IO_L10P_1,I/O,IO_L10P_1,I/O,IO_L10P_1,I/O,IO_L10P_1,I/O,1
+B,2,19,B19,IO_L06P_1,I/O,IO_L06P_1,I/O,IO_L06P_1,I/O,IO_L06P_1,I/O,1
+B,2,20,B20,IO_L01P_1/VRN_1,DCI,IO_L01P_1/VRN_1,DCI,IO_L01P_1/VRN_1,DCI,IO_L01P_1/VRN_1,DCI,1
+B,2,21,B21,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+B,2,22,B22,TDO,JTAG,TDO,JTAG,TDO,JTAG,TDO,JTAG,VCCAUX
+C,3,1,C1,IO_L16P_7/VREF_7,VREF,IO_L16P_7/VREF_7,VREF,IO_L16P_7/VREF_7,VREF,IO_L16P_7/VREF_7,VREF,7
+C,3,2,C2,IO,I/O,IO,I/O,IO,I/O,IO,I/O,7
+C,3,3,C3,IO_L01N_7/VRP_7,DCI,IO_L01N_7/VRP_7,DCI,IO_L01N_7/VRP_7,DCI,IO_L01N_7/VRP_7,DCI,7
+C,3,4,C4,IO_L01P_7/VRN_7,DCI,IO_L01P_7/VRN_7,DCI,IO_L01P_7/VRN_7,DCI,IO_L01P_7/VRN_7,DCI,7
+C,3,5,C5,IO_L06P_0,I/O,IO_L06P_0,I/O,IO_L06P_0,I/O,IO_L06P_0,I/O,0
+C,3,6,C6,IO_L15N_0,I/O,IO_L15N_0,I/O,IO_L15N_0,I/O,IO_L15N_0,I/O,0
+C,3,7,C7,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+C,3,8,C8,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+C,3,9,C9,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+C,3,10,C10,IO_L29N_0,I/O,IO_L29N_0,I/O,IO_L29N_0,I/O,IO_L29N_0,I/O,0
+C,3,11,C11,IO_L31P_0/VREF_0,VREF,IO_L31P_0/VREF_0,VREF,IO_L31P_0/VREF_0,VREF,IO_L31P_0/VREF_0,VREF,0
+C,3,12,C12,IO_L32P_1/GCLK4,GCLK,IO_L32P_1/GCLK4,GCLK,IO_L32P_1/GCLK4,GCLK,IO_L32P_1/GCLK4,GCLK,1
+C,3,13,C13,IO_L29N_1,I/O,IO_L29N_1,I/O,IO_L29N_1,I/O,IO_L29N_1,I/O,1
+C,3,14,C14,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+C,3,15,C15,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+C,3,16,C16,N.C.,N.C.,IO_L19N_1,I/O,IO_L19N_1,I/O,IO_L19N_1,I/O,1
+C,3,17,C17,IO_L16P_1,I/O,IO_L16P_1,I/O,IO_L16P_1,I/O,IO_L16P_1,I/O,1
+C,3,18,C18,IO_L09N_1,I/O,IO_L09N_1,I/O,IO_L09N_1,I/O,IO_L09N_1,I/O,1
+C,3,19,C19,IO_L01N_1/VRP_1,DCI,IO_L01N_1/VRP_1,DCI,IO_L01N_1/VRP_1,DCI,IO_L01N_1/VRP_1,DCI,1
+C,3,20,C20,IO_L01N_2/VRP_2,DCI,IO_L01N_2/VRP_2,DCI,IO_L01N_2/VRP_2,DCI,IO_L01N_2/VRP_2,DCI,2
+C,3,21,C21,IO_L01P_2/VRN_2,DCI,IO_L01P_2/VRN_2,DCI,IO_L01P_2/VRN_2,DCI,IO_L01P_2/VRN_2,DCI,2
+C,3,22,C22,IO,I/O,IO,I/O,IO,I/O,IO,I/O,2
+D,4,1,D1,IO_L16N_7,I/O,IO_L16N_7,I/O,IO_L16N_7,I/O,IO_L16N_7,I/O,7
+D,4,2,D2,IO_L19P_7,I/O,IO_L19P_7,I/O,IO_L19P_7,I/O,IO_L19P_7,I/O,7
+D,4,3,D3,IO_L19N_7/VREF_7,VREF,IO_L19N_7/VREF_7,VREF,IO_L19N_7/VREF_7,VREF,IO_L19N_7/VREF_7,VREF,7
+D,4,4,D4,IO_L17P_7,I/O,IO_L17P_7,I/O,IO_L17P_7,I/O,IO_L17P_7,I/O,7
+D,4,5,D5,IO_L06N_0,I/O,IO_L06N_0,I/O,IO_L06N_0,I/O,IO_L06N_0,I/O,0
+D,4,6,D6,IO_L10P_0,I/O,IO_L10P_0,I/O,IO_L10P_0,I/O,IO_L10P_0,I/O,0
+D,4,7,D7,IO_L16P_0,I/O,IO_L16P_0,I/O,IO_L16P_0,I/O,IO_L16P_0,I/O,0
+D,4,8,D8,N.C.,N.C.,IO_L22P_0,I/O,IO_L22P_0,I/O,IO_L22P_0,I/O,0
+D,4,9,D9,IO,I/O,IO,I/O,IO,I/O,IO,I/O,0
+D,4,10,D10,IO,I/O,IO,I/O,IO,I/O,IO,I/O,0
+D,4,11,D11,IO_L31N_0,I/O,IO_L31N_0,I/O,IO_L31N_0,I/O,IO_L31N_0,I/O,0
+D,4,12,D12,IO_L31N_1/VREF_1,VREF,IO_L31N_1/VREF_1,VREF,IO_L31N_1/VREF_1,VREF,IO_L31N_1/VREF_1,VREF,1
+D,4,13,D13,IO_L29P_1,I/O,IO_L29P_1,I/O,IO_L29P_1,I/O,IO_L29P_1,I/O,1
+D,4,14,D14,IO_L27N_1,I/O,IO_L27N_1,I/O,IO_L27N_1,I/O,IO_L27N_1,I/O,1
+D,4,15,D15,IO_L24N_1,I/O,IO_L24N_1,I/O,IO_L24N_1,I/O,IO_L24N_1,I/O,1
+D,4,16,D16,N.C.,N.C.,IO_L19P_1,I/O,IO_L19P_1,I/O,IO_L19P_1,I/O,1
+D,4,17,D17,IO_L15N_1,I/O,IO_L15N_1,I/O,IO_L15N_1,I/O,IO_L15N_1,I/O,1
+D,4,18,D18,IO_L09P_1,I/O,IO_L09P_1,I/O,IO_L09P_1,I/O,IO_L09P_1,I/O,1
+D,4,19,D19,IO_L16P_2,I/O,IO_L16P_2,I/O,IO_L16P_2,I/O,IO_L16P_2,I/O,2
+D,4,20,D20,IO_L16N_2,I/O,IO_L16N_2,I/O,IO_L16N_2,I/O,IO_L16N_2,I/O,2
+D,4,21,D21,IO_L17N_2,I/O,IO_L17N_2,I/O,IO_L17N_2,I/O,IO_L17N_2,I/O,2
+D,4,22,D22,IO_L17P_2/VREF_2,VREF,IO_L17P_2/VREF_2,VREF,IO_L17P_2/VREF_2,VREF,IO_L17P_2/VREF_2,VREF,2
+E,5,1,E1,IO_L21N_7,I/O,IO_L21N_7,I/O,IO_L21N_7,I/O,IO_L21N_7,I/O,7
+E,5,2,E2,IO_L21P_7,I/O,IO_L21P_7,I/O,IO_L21P_7,I/O,IO_L21P_7,I/O,7
+E,5,3,E3,IO_L20P_7,I/O,IO_L20P_7,I/O,IO_L20P_7,I/O,IO_L20P_7,I/O,7
+E,5,4,E4,IO_L17N_7,I/O,IO_L17N_7,I/O,IO_L17N_7,I/O,IO_L17N_7,I/O,7
+E,5,5,E5,N.C.,N.C.,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+E,5,6,E6,IO_L10N_0,I/O,IO_L10N_0,I/O,IO_L10N_0,I/O,IO_L10N_0,I/O,0
+E,5,7,E7,IO_L16N_0,I/O,IO_L16N_0,I/O,IO_L16N_0,I/O,IO_L16N_0,I/O,0
+E,5,8,E8,N.C.,N.C.,IO_L22N_0,I/O,IO_L22N_0,I/O,IO_L22N_0,I/O,0
+E,5,9,E9,IO_L25P_0,I/O,IO_L25P_0,I/O,IO_L25P_0,I/O,IO_L25P_0,I/O,0
+E,5,10,E10,IO_L28P_0,I/O,IO_L28P_0,I/O,IO_L28P_0,I/O,IO_L28P_0,I/O,0
+E,5,11,E11,IO_L30P_0,I/O,IO_L30P_0,I/O,IO_L30P_0,I/O,IO_L30P_0,I/O,0
+E,5,12,E12,IO_L31P_1,I/O,IO_L31P_1,I/O,IO_L31P_1,I/O,IO_L31P_1,I/O,1
+E,5,13,E13,IO/VREF_1,VREF,IO/VREF_1,VREF,IO/VREF_1,VREF,IO/VREF_1,VREF,1
+E,5,14,E14,IO_L27P_1,I/O,IO_L27P_1,I/O,IO_L27P_1,I/O,IO_L27P_1,I/O,1
+E,5,15,E15,IO_L24P_1,I/O,IO_L24P_1,I/O,IO_L24P_1,I/O,IO_L24P_1,I/O,1
+E,5,16,E16,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+E,5,17,E17,IO_L15P_1,I/O,IO_L15P_1,I/O,IO_L15P_1,I/O,IO_L15P_1,I/O,1
+E,5,18,E18,IO_L19N_2,I/O,IO_L19N_2,I/O,IO_L19N_2,I/O,IO_L19N_2,I/O,2
+E,5,19,E19,IO_L20N_2,I/O,IO_L20N_2,I/O,IO_L20N_2,I/O,IO_L20N_2,I/O,2
+E,5,20,E20,IO_L20P_2,I/O,IO_L20P_2,I/O,IO_L20P_2,I/O,IO_L20P_2,I/O,2
+E,5,21,E21,IO_L21N_2,I/O,IO_L21N_2,I/O,IO_L21N_2,I/O,IO_L21N_2,I/O,2
+E,5,22,E22,IO_L21P_2,I/O,IO_L21P_2,I/O,IO_L21P_2,I/O,IO_L21P_2,I/O,2
+F,6,1,F1,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+F,6,2,F2,IO_L23N_7,I/O,IO_L23N_7,I/O,IO_L23N_7,I/O,IO_L23N_7,I/O,7
+F,6,3,F3,IO_L23P_7,I/O,IO_L23P_7,I/O,IO_L23P_7,I/O,IO_L23P_7,I/O,7
+F,6,4,F4,IO_L20N_7,I/O,IO_L20N_7,I/O,IO_L20N_7,I/O,IO_L20N_7,I/O,7
+F,6,5,F5,IO_L22P_7,I/O,IO_L22P_7,I/O,IO_L22P_7,I/O,IO_L22P_7,I/O,7
+F,6,6,F6,IO,I/O,IO,I/O,IO,I/O,IO,I/O,0
+F,6,7,F7,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,IO/VREF_0,VREF,0
+F,6,8,F8,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,VCCO_0,VCCO,0
+F,6,9,F9,IO_L25N_0,I/O,IO_L25N_0,I/O,IO_L25N_0,I/O,IO_L25N_0,I/O,0
+F,6,10,F10,IO_L28N_0,I/O,IO_L28N_0,I/O,IO_L28N_0,I/O,IO_L28N_0,I/O,0
+F,6,11,F11,IO_L30N_0,I/O,IO_L30N_0,I/O,IO_L30N_0,I/O,IO_L30N_0,I/O,0
+F,6,12,F12,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+F,6,13,F13,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+F,6,14,F14,N.C.,N.C.,IO/VREF_1,VREF,IO/VREF_1,VREF,IO/VREF_1,VREF,1
+F,6,15,F15,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,VCCO_1,VCCO,1
+F,6,16,F16,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+F,6,17,F17,IO,I/O,IO,I/O,IO,I/O,IO,I/O,1
+F,6,18,F18,IO_L19P_2,I/O,IO_L19P_2,I/O,IO_L19P_2,I/O,IO_L19P_2,I/O,2
+F,6,19,F19,IO_L23N_2/VREF_2,VREF,IO_L23N_2/VREF_2,VREF,IO_L23N_2/VREF_2,VREF,IO_L23N_2/VREF_2,VREF,2
+F,6,20,F20,IO_L24N_2,I/O,IO_L24N_2,I/O,IO_L24N_2,I/O,IO_L24N_2,I/O,2
+F,6,21,F21,IO_L24P_2,I/O,IO_L24P_2,I/O,IO_L24P_2,I/O,IO_L24P_2,I/O,2
+F,6,22,F22,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+G,7,1,G1,IO_L27N_7,I/O,IO_L27N_7,I/O,IO_L27N_7,I/O,IO_L27N_7,I/O,7
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+AA,21,9,AA9,IO_L28P_5/D7,DUAL,IO_L28P_5/D7,DUAL,IO_L28P_5/D7,DUAL,IO_L28P_5/D7,DUAL,5
+AA,21,10,AA10,IO_L30P_5,I/O,IO_L30P_5,I/O,IO_L30P_5,I/O,IO_L30P_5,I/O,5
+AA,21,11,AA11,IO_L32N_5/GCLK3,GCLK,IO_L32N_5/GCLK3,GCLK,IO_L32N_5/GCLK3,GCLK,IO_L32N_5/GCLK3,GCLK,5
+AA,21,12,AA12,IO_L32N_4/GCLK1,GCLK,IO_L32N_4/GCLK1,GCLK,IO_L32N_4/GCLK1,GCLK,IO_L32N_4/GCLK1,GCLK,4
+AA,21,13,AA13,IO_L29P_4,I/O,IO_L29P_4,I/O,IO_L29P_4,I/O,IO_L29P_4,I/O,4
+AA,21,14,AA14,IO_L27N_4/DIN/D0,DUAL,IO_L27N_4/DIN/D0,DUAL,IO_L27N_4/DIN/D0,DUAL,IO_L27N_4/DIN/D0,DUAL,4
+AA,21,15,AA15,IO_L24N_4,I/O,IO_L24N_4,I/O,IO_L24N_4,I/O,IO_L24N_4,I/O,4
+AA,21,16,AA16,N.C.,N.C.,IO_L19N_4,I/O,IO_L19N_4,I/O,IO_L19N_4,I/O,4
+AA,21,17,AA17,IO_L15P_4,I/O,IO_L15P_4,I/O,IO_L15P_4,I/O,IO_L15P_4,I/O,4
+AA,21,18,AA18,IO_L09N_4,I/O,IO_L09N_4,I/O,IO_L09N_4,I/O,IO_L09N_4,I/O,4
+AA,21,19,AA19,N.C.,N.C.,IO_L05N_4,I/O,IO_L05N_4,I/O,IO_L05N_4,I/O,4
+AA,21,20,AA20,IO_L01N_4/VRP_4,DCI,IO_L01N_4/VRP_4,DCI,IO_L01N_4/VRP_4,DCI,IO_L01N_4/VRP_4,DCI,4
+AA,21,21,AA21,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+AA,21,22,AA22,CCLK,CONFIG,CCLK,CONFIG,CCLK,CONFIG,CCLK,CONFIG,VCCAUX
+AB,22,1,AB1,GND,GND,GND,GND,GND,GND,GND,GND,N/A
+AB,22,2,AB2,M0,CONFIG,M0,CONFIG,M0,CONFIG,M0,CONFIG,VCCAUX
+AB,22,3,AB3,M2,CONFIG,M2,CONFIG,M2,CONFIG,M2,CONFIG,VCCAUX
+AB,22,4,AB4,IO_L06N_5,I/O,IO_L06N_5,I/O,IO_L06N_5,I/O,IO_L06N_5,I/O,5
+AB,22,5,AB5,IO_L10N_5/VRP_5,DCI,IO_L10N_5/VRP_5,DCI,IO_L10N_5/VRP_5,DCI,IO_L10N_5/VRP_5,DCI,5
+AB,22,6,AB6,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+AB,22,7,AB7,N.C.,N.C.,IO_L22N_5,I/O,IO_L22N_5,I/O,IO_L22N_5,I/O,5
+AB,22,8,AB8,IO_L25N_5,I/O,IO_L25N_5,I/O,IO_L25N_5,I/O,IO_L25N_5,I/O,5
+AB,22,9,AB9,IO_L28N_5/D6,DUAL,IO_L28N_5/D6,DUAL,IO_L28N_5/D6,DUAL,IO_L28N_5/D6,DUAL,5
+AB,22,10,AB10,IO_L30N_5,I/O,IO_L30N_5,I/O,IO_L30N_5,I/O,IO_L30N_5,I/O,5
+AB,22,11,AB11,IO/VREF_5,VREF,IO/VREF_5,VREF,IO/VREF_5,VREF,IO/VREF_5,VREF,5
+AB,22,12,AB12,IO_L32P_4/GCLK0,GCLK,IO_L32P_4/GCLK0,GCLK,IO_L32P_4/GCLK0,GCLK,IO_L32P_4/GCLK0,GCLK,4
+AB,22,13,AB13,IO/VREF_4,VREF,IO/VREF_4,VREF,IO/VREF_4,VREF,IO/VREF_4,VREF,4
+AB,22,14,AB14,IO_L27P_4/D1,DUAL,IO_L27P_4/D1,DUAL,IO_L27P_4/D1,DUAL,IO_L27P_4/D1,DUAL,4
+AB,22,15,AB15,IO_L24P_4,I/O,IO_L24P_4,I/O,IO_L24P_4,I/O,IO_L24P_4,I/O,4
+AB,22,16,AB16,N.C.,N.C.,IO_L19P_4,I/O,IO_L19P_4,I/O,IO_L19P_4,I/O,4
+AB,22,17,AB17,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,VCCAUX,N/A
+AB,22,18,AB18,IO_L09P_4,I/O,IO_L09P_4,I/O,IO_L09P_4,I/O,IO_L09P_4,I/O,4
+AB,22,19,AB19,N.C.,N.C.,IO_L05P_4,I/O,IO_L05P_4,I/O,IO_L05P_4,I/O,4
+AB,22,20,AB20,IO_L01P_4/VRN_4,DCI,IO_L01P_4/VRN_4,DCI,IO_L01P_4/VRN_4,DCI,IO_L01P_4/VRN_4,DCI,4
+AB,22,21,AB21,DONE,CONFIG,DONE,CONFIG,DONE,CONFIG,DONE,CONFIG,VCCAUX
+AB,22,22,AB22,GND,GND,GND,GND,GND,GND,GND,GND,N/A

Modified: usrp-hw/trunk/sym/generated/make_symbols
===================================================================
--- usrp-hw/trunk/sym/generated/make_symbols    2006-09-11 18:53:50 UTC (rev 
3521)
+++ usrp-hw/trunk/sym/generated/make_symbols    2006-09-11 19:36:23 UTC (rev 
3522)
@@ -130,3 +130,18 @@
 tragesym irm046u-LB.src irm046u-LB.sym
 tragesym irm046u-HB.src irm046u-HB.sym
 tragesym irm046u-PWR.src irm046u-PWR.sym
+
+./xilinxgen
+tragesym xc3sXX00FG456-IO0.src xc3sXX00FG456-IO0.sym
+tragesym xc3sXX00FG456-IO1.src xc3sXX00FG456-IO1.sym
+tragesym xc3sXX00FG456-IO2.src xc3sXX00FG456-IO2.sym
+tragesym xc3sXX00FG456-IO3.src xc3sXX00FG456-IO3.sym
+tragesym xc3sXX00FG456-IO4.src xc3sXX00FG456-IO4.sym
+tragesym xc3sXX00FG456-IO5.src xc3sXX00FG456-IO5.sym
+tragesym xc3sXX00FG456-IO6.src xc3sXX00FG456-IO6.sym
+tragesym xc3sXX00FG456-IO7.src xc3sXX00FG456-IO7.sym
+tragesym xc3sXX00FG456-PWR.src xc3sXX00FG456-PWR.sym
+tragesym xc3sXX00FG456-CFG.src xc3sXX00FG456-CFG.sym
+tragesym xc3sXX00FG456-CLK.src xc3sXX00FG456-CLK.sym
+tragesym xc3sXX00FG456-JTAG.src xc3sXX00FG456-JTAG.sym
+tragesym xc3sXX00FG456-VREF.src xc3sXX00FG456-VREF.sym

Added: usrp-hw/trunk/sym/generated/xilinxgen
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen                               (rev 0)
+++ usrp-hw/trunk/sym/generated/xilinxgen       2006-09-11 19:36:23 UTC (rev 
3522)
@@ -0,0 +1,122 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+    newname = matchstr.sub("\\_",name)
+    file.write("%s\t\t%s\t%s\t%s\t\t%s\n" % 
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('fg456_table.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20030525
+name=XC3SXX00FG456-%s
+device=XC3SXX00FG456
+refdes=U?
+footprint=FG456
+description=Xilinx Spartan 3 400/1000/1500/2000 FG456
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3sXX00FG456-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3sXX00FG456-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3sXX00FG456-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+clockfile = open ('xc3sXX00FG456-CLK.src', 'w')
+clockfile.write(boilerplate % ("CLK",))
+vreffile = open ('xc3sXX00FG456-VREF.src', 'w')
+vreffile.write(boilerplate % ("VREF",))
+
+iofiles = [0] * 8
+for i in range(8):
+    iofiles[i] = open ( ('xc3sXX00FG456-IO%d.src' % (i,)), 'w')
+    iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+    
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+    elements = line.strip().split(',')
+
+    pintype = elements[7]
+    nc = elements[5] == "N.C."
+
+    if(elements[5] != elements[9]) and not nc:
+        print "error"
+        print elements
+
+    if nc and pintype != 'I/O' and pintype != 'VREF':
+        print "error"
+        print elements
+    
+
+    if(pintype == 'GND'):
+        writepin(powerfile,elements[3],elements[6],'line','pwr','r')
+    elif(pintype == 'VCCAUX'):
+        writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+    elif(pintype == 'VCCO'):
+        writepin(powerfile,elements[3],elements[6],'line','pwr','t')
+    elif(pintype == 'VCCINT'):
+        writepin(powerfile,elements[3],elements[6],'line','pwr','b')
+
+    elif(pintype == 'JTAG'):
+        writepin(jtagfile,elements[3],elements[6],'line','io','l')
+
+    elif(pintype == 'CONFIG'):
+        writepin(configfile,elements[3],elements[6],'line','io','l')
+
+    elif(pintype == 'DUAL'):
+        writepin(configfile,elements[3],elements[6],'line','io','r')
+
+    elif(pintype == 'GCLK'):
+        writepin(clockfile,elements[3],elements[6],'clk','clk','l')
+
+    elif(pintype == 'VREF'):
+        if nc:
+            writepin(vreffile,elements[3],"%s/400NC" % 
(elements[6],),'line','io','r')
+        else:
+            writepin(vreffile,elements[3],elements[6],'line','io','l')
+
+    elif(pintype == 'I/O'):
+        if nc:
+            writepin(iofiles[int(elements[12])],elements[3],"%s/400NC" % 
(elements[6],),'line','io','r')
+        else:
+            
writepin(iofiles[int(elements[12])],elements[3],elements[6],'line','io','l')
+
+    elif(pintype == 'DCI'):
+        writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" % 
(elements[6],),'line','io','l')
+
+    else:
+        print elements
+
+
+
+    #vreffile.write("%s\t\tio\tpwr\tl\t\t%s/400-NC\n" % 
(elements[3],elements[6]))
+#iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/400-NC\n" % 
(elements[3],elements[6]))
+#iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s\n" % 
(elements[3],elements[4]))
+        #iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/DCI\n" % 
(elements[3],elements[4]))
+        #vreffile.write("%s\t\tio\tpwr\tl\t\t%s\n" % (elements[3],elements[4]))
+        #powerfile.write("%s\t\tpwr\tline\tr\t\t%s\n" % 
(elements[3],elements[4]))
+        #powerfile.write("%s\t\tpwr\tline\tl\t\t%s\n" % 
(elements[3],elements[4]))
+        #powerfile.write("%s\t\tpwr\tline\tt\t\t%s\n" % 
(elements[3],elements[4]))
+        #powerfile.write("%s\t\tpwr\tline\tb\t\t%s\n" % 
(elements[3],elements[4]))
+        #jtagfile.write("%s\t\tio\tline\tl\t\t%s\n" % 
(elements[3],elements[4]))
+        #configfile.write("%s\t\tio\tline\tl\t\t%s\n" % 
(elements[3],elements[4]))
+        #configfile.write("%s\t\tio\tline\tr\t\t%s\n" % 
(elements[3],elements[4]))
+        #clockfile.write("%s\t\tio\tclk\tl\t\t%s\n" % 
(elements[3],elements[4]))


Property changes on: usrp-hw/trunk/sym/generated/xilinxgen
___________________________________________________________________
Name: svn:executable
   + *
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