[Commit-gnuradio] r4822 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-03-29 17:31:05 -0600 (Thu, 29 Mar 2007)
New Revision: 4822

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
first cut at entering all pins


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-03-29 22:41:56 UTC (rev 4821)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-03-29 23:31:05 UTC (rev 4822)
@@ -18,9 +18,151 @@
 // Additional Comments: 
 //
 
//////////////////////////////////////////////////////////////////////////////////
-module u2_basic(a,b
-        );
-input a;
-output b;
+module u2_basic
+  (
 
-endmodule
+   // Misc, debug
+   output led1,
+   output led2,
+   output [31:0] debug,
+   output [1:0] debug_clk,
+
+   // Expansion
+   input exp_pps_in, // Diff
+   output exp_pps_out, // Diff 
+   
+   // GMII
+   //   GMII-CTRL
+   input GMII_COL,
+   input GMII_CRS,
+
+   //   GMII-TX
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
+   output GMII_TX_CLK,  // 100mbps clk
+
+   //   GMII-RX
+   input [7:0] GMII_RXD,
+   input GMII_RX_CLK,
+   input GMII_RX_DV,
+   input GMII_RX_ER,
+
+   //   GMII-Management
+   inout MDIO,
+   output MDC,
+   input PHY_INTn,   // open drain
+   output PHY_RESETn,
+   output PHY_CLK,   // possibly use on-board osc
+
+   // RAM
+   inout RAM_D[17:0],
+   output RAM_A[18:0],
+   output RAM_CE1n,
+   output RAM_CENn,
+   output RAM_CLK,
+   output RAM_WEn,
+   output RAM_OEn,
+   output RAM_LDn,
+   
+   // SERDES
+   output ser_enable,
+   output ser_prbsen,
+   output ser_loopen,
+   
+   output ser_tx_clk,
+   output ser_t[15:0],
+   output ser_tklsb,
+   output ser_tkmsb,
+
+   input ser_rx_clk,
+   output ser_rx_en,
+   input ser_r[15:0],
+   input ser_rklsb,
+   input ser_rkmsb,
+   
+   // CPLD interface
+   output spi_cpld_en,
+   output spi_cpld_dout,
+   input spi_cpld_din,
+   output spi_cpld_clk,
+   
+   // ADC
+   input [13:0] adc_a,
+   input adc_ovf_a,
+   output adc_oen_a,
+   output adc_pdn_a,
+   
+   input [13:0] adc_b,
+   input adc_ovf_b,
+   output adc_oen_b,
+   output adc_pdn_b,
+   
+   // DAC
+   output [15:0] dac_a,
+   output [15:0] dac_b,
+
+   
+   // I2C
+   inout SCL,
+   inout SDA,
+   output SCL_force,
+   output SDA_force,
+
+   // Clock Gen Control
+   output clk_en[1:0],
+   output clk_sel[1:0],
+   input clk_func,
+   input clk_status,
+
+   // Clocks
+   input clk_fpga,  // Diff
+   input clk_to_mac,
+   input pps_in,
+   
+   // Generic SPI
+   output sclk,
+   output sen_clk,
+   output sen_dac,
+   output sdi,
+   input sdo,
+   
+   // TX DBoard
+   output sen_tx_db,
+   output sclk_tx_db,
+   output sdo_tx_db,
+   input sdi_tx_db,
+
+   output sen_tx_adc,
+   output sclk_tx_adc,
+   output sdo_tx_adc,
+   input sdi_tx_adc,
+
+   output sen_tx_dac,
+   output sclk_tx_dac,
+   output sdi_tx_dac,
+
+   inout io_tx[15:0],
+
+   // RX DBoard
+   output sen_rx_db,
+   output sclk_rx_db,
+   output sdo_rx_db,
+   input sdi_rx_db,
+
+   output sen_rx_adc,
+   output sclk_rx_adc,
+   output sdo_rx_adc,
+   input sdi_rx_adc,
+
+   output sen_rx_dac,
+   output sclk_rx_dac,
+   output sdi_rx_dac,
+
+   inout io_rx[15:0]
+   
+   );
+   
+endmodule // u2_basic
+