[Commit-gnuradio] r4837 - in gnuradio/branches/developers/matt/u2f: . control_lib

[matt]

Author: matt
Date: 2007-03-31 19:39:08 -0600 (Sat, 31 Mar 2007)
New Revision: 4837

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/
   gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
   gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.sav
   gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.v
Log:
basic clock control for bootstrapping the clock


Added: gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v           
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v   
2007-04-01 01:39:08 UTC (rev 4837)
@@ -0,0 +1,102 @@
+
+
+// AD9510 Register Map (from datasheet Rev. A)
+
+/* INSTRUCTION word format (16 bits)
+ * 15       Read = 1, Write = 0
+ * 14:13    W1/W0,  Number of bytes 00 - 1, 01 - 2, 10 - 3, 11 - stream
+ * 12:0     Address
+ */
+
+/* ADDR     Contents             Value (hex)
+ * 00       Serial Config Port   10 (def) -- MSB first, SDI/SDO separate
+ * 04       A Counter
+ * 05-06    B Counter
+ * 07-0A    PLL Control
+ * 0B-0C    R Divider
+ * 0D       PLL Control
+ * 34-3A    Fine Delay
+ * 3C-3F    LVPECL Outs
+ * 40-43    LVDS/CMOS Outs
+ * 45       Clock select, power down
+ * 48-57    Dividers
+ * 58       Func and Sync
+ * 5A       Update regs
+ */
+
+
+module clock_control
+  (input reset,
+   input aux_clk,            // 25MHz, for before fpga clock is active
+   input clk_fpga,           // real 100 MHz FPGA clock
+   output [1:0] clk_en,      // controls source of reference clock
+   output [1:0] clk_sel,     // controls source of reference clock
+   output clk_func,          // SYNC or reset to 9510
+   input clk_status,         // Monitor PLL or SYNC status
+      
+   output sen,        // Enable for the AD9510
+   output sclk,       // FIXME these need to be shared
+   output sdi,
+   output sdo
+   );
+
+   wire   read = 1'b0;    // Always write for now
+   wire [1:0] w = 2'b00;  // Always send 1 byte at a time
+   
+   reg [20:0]  addr_data;
+   //   reg [7:0]   data;
+   reg [5:0]   entry;
+   reg                start;
+   reg [7:0]   counter;
+   reg [23:0]  command;
+   
+   always @*
+     case(entry)
+       6'd00 : addr_data = {13'h00,8'h10};   // Serial setup
+       6'd01 : addr_data = {13'h0B,8'h00};   // R-Div MSB
+       6'd02 : addr_data = {13'h0C,8'h0A};   // R-Div LSB (R = 10)
+       default : addr_data = {13'h1FFF,8'h00};
+     endcase // case(entry)
+
+   wire [5:0]  lastentry = 6'd2;
+              
+   always @(posedge aux_clk)
+     if(reset)
+       begin
+         entry <= #1 6'd0;
+         start <= #1 1'b1;
+       end
+     else if(start)
+       start <= #1 1'b0;
+     else if(done && (entry<lastentry))
+       begin
+         entry <= #1 entry + 6'd1;
+         start <= #1 1'b1;
+       end
+   
+   always @(posedge aux_clk)
+     if(reset)
+       begin
+         counter <= #1 7'd0;
+         command <= #1 20'd0;
+       end
+     else if(start)
+       begin
+         counter <= #1 7'd1;
+         command <= #1 {read,w,addr_data};
+       end
+     else if( |counter && ~done )
+       begin
+         counter <= #1 counter + 7'd1;
+         if(~counter[0])
+           command <= {command[22:0],1'b0};
+       end
+
+   wire done = (counter == 8'd49);
+   
+   assign sen = (done | counter == 8'd0);  // CSB is high when we're not doing 
anything
+   assign sclk = ~counter[0];
+   assign sdo = command[23];
+   
+
+endmodule // clock_control

Added: gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.sav
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.sav      
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.sav      
2007-04-01 01:39:08 UTC (rev 4837)
@@ -0,0 +1,28 @@
+[size] 1400 971
+[pos] -1 -1
+*-7.848898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1
address@hidden
+clock_control_tb.aux_clk
+clock_control_tb.reset
+clock_control_tb.sclk
+clock_control_tb.sdi
+clock_control_tb.sdo
+clock_control_tb.sen
address@hidden
+clock_control_tb.clock_control.counter[7:0]
address@hidden
+clock_control_tb.clock_control.done
address@hidden
+clock_control_tb.clock_control.entry[5:0]
address@hidden
+clock_control_tb.clock_control.read
+clock_control_tb.clock_control.reset
+clock_control_tb.clock_control.sclk
+clock_control_tb.clock_control.w[1:0]
+clock_control_tb.sen
+clock_control_tb.sdo
+clock_control_tb.sclk
+clock_control_tb.clock_control.done
+clock_control_tb.clock_control.start
address@hidden
+clock_control_tb.clock_control.addr_data[20:0]

Added: gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.v        
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control_tb.v        
2007-04-01 01:39:08 UTC (rev 4837)
@@ -0,0 +1,35 @@
+
+
+module clock_control_tb();
+   
+  clock_control clock_control
+    (.reset(reset),
+     .aux_clk(aux_clk),  
+     .clk_fpga(clk_fpga),
+     .clk_en(clk_en),    
+     .clk_sel(clk_sel),  
+     .clk_func(clk_func), 
+     .clk_status(clk_status),
+     
+     .sen(sen),   
+     .sclk(sclk), 
+     .sdi(sdi),
+     .sdo(sdo)
+     );
+
+   reg reset, aux_clk;
+   
+   wire [1:0] clk_sel, clk_en;
+   
+   initial reset = 1'b1;
+   initial #1000 reset = 1'b0;
+   
+   initial aux_clk = 1'b0;
+   always #10 aux_clk = ~aux_clk;
+   
+   initial $dumpfile("clock_control_tb.vcd");
+   initial $dumpvars(0,clock_control_tb);
+   
+   initial #10000 $finish;
+   
+endmodule // clock_control_tb