[Commit-gnuradio] r4866 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga: . usrp_std

[jcorgan]

Author: jcorgan
Date: 2007-04-03 19:55:52 -0600 (Tue, 03 Apr 2007)
New Revision: 4866

Added:
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std_assignment_defaults.qdf
Modified:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/config.vh
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.qsf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.v
Log:
Recreated usrp_std project, synthesizes without error.

Copied: gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std 
(from rev 4863, 
gnuradio/branches/developers/jcorgan/sar-fe/usrp/fpga/toplevel/usrp_std)


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std
___________________________________________________________________
Name: svn:ignore
   + *.qws
*.eqn
*.done
*.htm
*.rpt
*.ini
*.fsf
*.jam
*.jbc
*.pin
*.pof
*.smsg
*.sof
*.rbf
*.ttf
*.summary
db


Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/config.vh
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/usrp/fpga/toplevel/usrp_std/config.vh
   2007-04-03 22:39:02 UTC (rev 4863)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/config.vh
   2007-04-04 01:55:52 UTC (rev 4866)
@@ -34,7 +34,7 @@
 //`include "../include/common_config_1rxhb_1tx.vh"
 
 // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-  `include "../include/common_config_2rxhb_2tx.vh"
+  `include "../../../../usrp/fpga/toplevel/include/common_config_2rxhb_2tx.vh"
 
 // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
 //`include "../include/common_config_4rx_0tx.vh"
@@ -50,4 +50,4 @@
 // ====================================================================
 //  Now include the common footer
 // ====================================================================
-  `include "../include/common_config_bottom.vh"
+  `include "../../../../usrp/fpga/toplevel/include/common_config_bottom.vh"

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
        2007-04-03 22:39:02 UTC (rev 4863)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.qsf
        2007-04-04 01:55:52 UTC (rev 4866)
@@ -27,7 +27,7 @@
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04  JULY 13, 
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION 7.0
 
 # Pin & Location Assignments
 # ==========================
@@ -222,7 +222,7 @@
 set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE SPEED
 set_global_assignment -name TOP_LEVEL_ENTITY usrp_std
 set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name USER_LIBRARIES "e:\\usrp\\fpga\\megacells"
+set_global_assignment -name USER_LIBRARIES 
"h:\\gnuradio\\trunk\\usrp\\fpga\\megacells"
 set_global_assignment -name AUTO_ENABLE_SMART_COMPILE ON
 
 # Fitter Assignments
@@ -368,39 +368,41 @@
 # end ENTITY(usrp_std)
 # --------------------
 
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_ram.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cic_dec_shifter.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/acc.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/hb/ram16_2sum.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/hb/coeff_rom.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/hb/halfband_decim.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/hb/mac.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/hb/coeff_ram.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/tx_chain.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/io_pins.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/megacells/clk_doubler.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/master_control.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/megacells/fifo_2k.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/megacells/bustri.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/tx_buffer.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cic_decim.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
 set_global_assignment -name VERILOG_FILE usrp_std.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/strobe_gen.v
+set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/sign_extend.v
+set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition 
-to | -section_id Top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
\ No newline at end of file

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/usrp/fpga/toplevel/usrp_std/usrp_std.v
  2007-04-03 22:39:02 UTC (rev 4863)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std.v
  2007-04-04 01:55:52 UTC (rev 4866)
@@ -28,8 +28,8 @@
 // Uncomment the following to include optional circuitry
 
 `include "config.vh"
-`include "../../../firmware/include/fpga_regs_common.v"
-`include "../../../firmware/include/fpga_regs_standard.v"
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
 
 module usrp_std
 (output MYSTERY_SIGNAL,

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std_assignment_defaults.qdf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std_assignment_defaults.qdf
                            (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std_assignment_defaults.qdf
    2007-04-04 01:55:52 UTC (rev 4866)
@@ -0,0 +1,415 @@
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name RTLV_PRESERVED_HANGING_NODES Off
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name INCREMENTAL_COMPILATION -value 
FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name INCREMENTAL_COMPILATION_EXPORT_NETLIST_TYPE 
POST_FIT
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY On
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION On
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name 
SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name 
SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_INCREMENTAL_TIME_INPUT Off
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output 
driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular 
IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as 
programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as 
regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as 
regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION 
"Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input 
tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular 
IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input 
tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION 
"Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input 
tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as 
regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as 
programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD 
Paths"
+set_global_assignment -name OPTIMIZE_FAST_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING On
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 
Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING 
Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name 
ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name 
STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE 
Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name 
STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name 
STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name 
STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name 
STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name 
STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input 
tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL93
+set_global_assignment -name FAMILY Stratix
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 
Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_GATE_RETIME Off
+set_global_assignment -name ADV_NETLIST_OPT_RETIME_CORE_AND_IO On
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION On
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name 
STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SHOW_PARAMETER_SETTINGS_TABLES_IN_SYNTHESIS_REPORT 
On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name ADV_NETLIST_OPT_METASTABLE_REGS 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal 
compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name SUPPRESS_REG_MINIMIZATION_MSG Off
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 100
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name IGNORE_CLOCK_SETTINGS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS Off
+set_global_assignment -name ENABLE_CLOCK_LATENCY Off
+set_global_assignment -name NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_DESTINATION_TO_REPORT 10
+set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 200
+set_global_assignment -name DO_MIN_ANALYSIS Off
+set_global_assignment -name DO_MIN_TIMING Off
+set_global_assignment -name REPORT_IO_PATHS_SEPARATELY Off
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_HCII_COMPARE Off
+set_global_assignment -name HCII_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name MAX_PROCESSORS_USED_FOR_MULTITHREADING 1
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 
-section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id 
?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All 
Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF 
-section_id ?
+set_global_assignment -name 
EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "100 ns" -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id 
?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? 
-entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS 
REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS 
REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On 
-section_id ? -entity ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/usrp_std/usrp_std_assignment_defaults.qdf
___________________________________________________________________
Name: svn:executable
   + *