[Commit-gnuradio] r4889 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/lib fpga/toplevel python

[jcorgan]

Author: jcorgan
Date: 2007-04-05 18:56:08 -0600 (Thu, 05 Apr 2007)
New Revision: 4889

Added:
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_rx.v
Modified:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py
Log:
Work in progress.  Stubbed out sar_rx block, can receive counter values on host.

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_rx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_rx.v 
                        (rev 0)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_rx.v 
2007-04-06 00:56:08 UTC (rev 4889)
@@ -0,0 +1,72 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+`include "../../../../usrp/firmware/include/fpga_regs_common.v"
+`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+
+module 
sar_rx(clk_i,rst_i,ena_i,strobe_i,saddr_i,sdata_i,s_strobe_i,cpi_i,rx_in_i_i,rx_in_q_i,rx_i_o,rx_q_o,rx_strobe_o,debug_o);
+   input clk_i;
+   input rst_i;
+   input ena_i;
+   input strobe_i;
+
+   input [6:0] saddr_i;
+   input [31:0] sdata_i;
+   input s_strobe_i;
+
+   input [7:0] cpi_i;
+   input [15:0] rx_in_i_i;
+   input [15:0] rx_in_q_i;
+
+   output [15:0] rx_i_o;
+   output [15:0] rx_q_o;
+   output rx_strobe_o;
+   output [15:0] debug_o;
+
+   // Just count up for debugging
+   reg [31:0] counter;
+
+   always @(posedge clk_i)
+     begin
+       if (rst_i | ~ena_i)
+         counter <= 32'b0;
+       else if (strobe_i & rx_strobe_o)
+         counter <= counter + 32'b1;
+     end
+
+   assign rx_i_o = ena_i ? counter[31:16] : 16'b0;
+   assign rx_q_o = ena_i ? counter[15:0] : 16'b0;
+   assign debug_o = 16'hAA55;
+   
+   // Temporarily we duplicate what master_control.v did to generate 
decim_strobe
+   // so we can do receive debugging. Later we'll drive rx_strobe_o in bursts 
to
+   // load receiver data into the rx fifo.
+   strobe_gen rx_strobe_gen
+         ( .clock(clk_i),
+               .reset(rst_i),
+               .enable(ena_i),
+        .rate(cpi_i),
+        .strobe_in(strobe_i),
+        .strobe(rx_strobe_o) 
+      );
+   
+endmodule // sar_rx
+


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_rx.v
___________________________________________________________________
Name: svn:executable
   + *

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
        2007-04-06 00:18:58 UTC (rev 4888)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
        2007-04-06 00:56:08 UTC (rev 4889)
@@ -370,6 +370,7 @@
 
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition 
-to | -section_id Top
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE ../lib/sar_rx.v
 set_global_assignment -name VERILOG_FILE ../lib/sar_tx.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_buffer.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/setting_reg.v

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-06 00:18:58 UTC (rev 4888)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-06 00:56:08 UTC (rev 4889)
@@ -72,10 +72,10 @@
    assign usbrdy[0] = 1'b0; // have_space;
    assign usbrdy[1] = have_pkt_rdy;
 
-   wire   tx_underrun, rx_overrun;    
+   wire   rx_overrun;    
    wire   clear_status = FX2_1;
    assign FX2_2 = rx_overrun;
-   assign FX2_3 = tx_underrun;
+   assign FX2_3 = 1'b0; // tx_underrun;
       
    wire [15:0] usbdata_out;
 
@@ -137,15 +137,17 @@
                               
.ddc3_in_i(),.ddc3_in_q(),.rx_numchan(rx_numchan));
 
 
-   // Put sar_rx block here, reading rx_in_i, rx_in_q
-   // and drives rx_i, rx_q, rx_debug
+
    wire [15:0] rx_i, rx_q;
+   wire        rx_strobe;
    wire [15:0] rx_debug;
+
+   sar_rx 
receiver(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_rx),.strobe_i(rx_sample_strobe),
+                  
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
+                  .cpi_i(decim_rate),.rx_in_i_i(rx_in_i),.rx_in_q_i(rx_in_q), 
// we use decim_rate for convenience as CPI
+                  
.rx_i_o(rx_i),.rx_q_o(rx_q),.rx_strobe_o(rx_strobe),.debug_o(rx_debug));
    
-   assign rx_i = 16'hDEAD;
-   assign rx_q = 16'hBEEF;
-   assign rx_debug = 16'hABCD;
-   
+
    rx_buffer rx_buffer
      ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
        .reset_regs(rx_dsp_reset),
@@ -155,10 +157,10 @@
        .ch_2(),.ch_3(),
        .ch_4(),.ch_5(),
        .ch_6(),.ch_7(),
-       .rxclk(clk64),.rxstrobe(rx_sample_strobe),
+       .rxclk(clk64),.rxstrobe(rx_strobe), // Note this is generated in bursts 
from sar_rx
        .clear_status(clear_status),
        
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
-       .debugbus(rx_debugbus));
+       .debugbus());
 
 
    
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
@@ -187,7 +189,7 @@
        .enable_tx(enable_tx),.enable_rx(enable_rx),
        .interp_rate(interp_rate),.decim_rate(decim_rate),
        .tx_sample_strobe(tx_sample_strobe),.strobe_interp(strobe_interp),
-       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
+       .rx_sample_strobe(rx_sample_strobe),.strobe_decim(), // Note we don't 
use the strobe_decim output from here
        .tx_empty(tx_empty),
        .debug_0(),.debug_1(),.debug_2(tx_debug),.debug_3(rx_debug),
        .reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3));

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py   
    2007-04-06 00:18:58 UTC (rev 4888)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py   
    2007-04-06 00:56:08 UTC (rev 4889)
@@ -1,12 +1,26 @@
 #!/usr/bin/env python
 
-from gnuradio import usrp
+from gnuradio import gr, usrp
 
-def main():
+def test_transmit():
     transmitter = usrp.sink_c(fpga_filename = 'usrp_sar.rbf')
     transmitter.start()
-    raw_input()
+    raw_input('Press return to stop transmitter.')
     transmitter.stop()
+
+def test_receive():
+    fg = gr.flow_graph()
+    src = usrp.source_s(fpga_filename = 'usrp_sar.rbf',decim_rate=256)
+    src.set_mux(usrp.determine_rx_mux_value(src, (0,0)))
+    head = gr.head(gr.sizeof_short, 500000)
+    dst = gr.file_sink(gr.sizeof_short, 'output.dat')
+    fg.connect(src, head, dst)
+    fg.run()
+
+
+def main():
+    test_transmit()
+    test_receive()
     
 if __name__ == "__main__":
     main()