[Commit-gnuradio] r4901 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/lib fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python

[jcorgan]

Author: jcorgan
Date: 2007-04-06 17:29:36 -0600 (Fri, 06 Apr 2007)
New Revision: 4901

Modified:
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py
Log:
Work in progress.  Now driving the tx at 64 MHz, but feeding the samples to the
9862 DAC is still probably not right.  In the absence of CLKOUT1 or 2 from the 
9862
being brought in to the FPGA, the master_clk is used as the driver of TxSYNC and
the I and Q bus multiplexer.  It's working, but seeing some odd behavior of the
cordic at high frequencies.  This also requires host code to poke different 
values
into the TX_IF and TX_DIGITAL registers of the 9862.


Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v 
2007-04-06 19:57:55 UTC (rev 4900)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v 
2007-04-06 23:29:36 UTC (rev 4901)
@@ -36,15 +36,16 @@
    output [15:0] tx_q_o;
    output [15:0] debug_o;
 
-   // Full scale sine wave @ maximum frequency
-   wire [15:0]          mag   = 16'h7FFF;
-   wire [31:0]          freq  = 32'h7FFFFFFF;
-   wire [31:0]          phase = 32'b0;
+   wire [31:0]          mag, freq, phase;
+   setting_reg #(`FR_USER_0) 
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag));
+   setting_reg #(`FR_USER_1) 
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq));
+   setting_reg #(`FR_USER_2) 
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phase));
+   
    wire [15:0]          data_i_o;
    wire [15:0]          data_q_o;
    
    cordic_nco 
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
-                 .mag_i(mag),.freq_i(freq),.phs_i(phase),
+                 .mag_i(mag[15:0]),.freq_i(freq),.phs_i(phase),
                  .data_i_o(data_i_o),.data_q_o(data_q_o));
 
    assign tx_i_o = ena_i ? data_i_o : 16'b0;

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-06 19:57:55 UTC (rev 4900)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-06 23:29:36 UTC (rev 4901)
@@ -62,7 +62,7 @@
    wire [15:0] debugdata,debugctrl;
    assign MYSTERY_SIGNAL = 1'b0;
    
-   wire clk64,clk128;
+   wire clk64;
    
    wire WR = usbctl[0]; // Not used
    wire RD = usbctl[1];
@@ -109,18 +109,20 @@
    wire [15:0] tx_i, tx_q;
    wire [15:0] tx_debug;
    
-   // Multiplex tx_i and tx_q onto TXA DAC pins
-   assign tx_a = tx_sample_strobe ? tx_q[15:2] : tx_i[15:2];
-   assign TXSYNC_A = tx_sample_strobe;
+   // Transmitter creates a new output sample per clk64
+   sar_tx 
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(1'b1),
+                     
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
+                     .tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
 
-   // Wedge TXB at zero
+   // This requires (in addition to the default setup in usrp_basic.cc) that
+   // the AD9862 has sampling enabled on two edges and no interpolation
+   // TX_IF = 8'h4B, TX_DIGITAL = 8'h10
+   assign TXSYNC_A = clk64;
+   assign tx_a = clk64 ? tx_i[15:2] : tx_q[15:2];
+
    assign tx_b = 14'b0;
    assign TXSYNC_B = 0;
    
-   sar_tx 
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(tx_sample_strobe),
-                     
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
-                     .tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
-
    
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Receive Side
 

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py   
    2007-04-06 19:57:55 UTC (rev 4900)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/debug_sar.py   
    2007-04-06 23:29:36 UTC (rev 4901)
@@ -1,14 +1,46 @@
 #!/usr/bin/env python
 
 from gnuradio import gr, usrp
+from gnuradio import eng_notation
+from gnuradio.eng_option import eng_option
+from optparse import OptionParser
+import math
 
-def test_transmit():
-    transmitter = usrp.sink_c(fpga_filename = 'usrp_sar.rbf')
-    transmitter.start()
+class sar_tx:
+    def __init__(self):
+       self.trans = usrp.sink_s(fpga_filename='usrp_sar.rbf')
+       self.trans._write_9862(0, 18, 0x4B)  # Sample two edges
+       self.trans._write_9862(0, 19, 0x10)  # Turn off interpolation
+       
+    def set_amplitude(self, amplitude):
+       self.trans._write_fpga_reg(usrp.FR_USER_0, int(amplitude))
+
+    def tune(self, freq):
+       ftw = int(freq*(2**32)/64e6)
+       self.trans._write_fpga_reg(usrp.FR_USER_1, ftw)
+
+    def set_phase(self, phase):
+        ptw = int(float(2**32)*phase/(2.0*math.pi))
+       self.trans._write_fpga_reg(usrp.FR_USER_2, ptw)
+    
+    def start(self):
+       self.trans.start()
+       
+    def stop(self):
+       self.trans.stop()
+
+def test_transmit(options):
+    t = sar_tx()
+    t.set_amplitude(options.amplitude)
+    t.tune(options.frequency)
+    t.set_phase(options.phase)
+    t.start()
     raw_input('Press return to stop transmitter.')
-    transmitter.stop()
+    t.stop
 
 def test_receive():
+    # This captures the output of the debug counter in sar_rx
+    # It will run for 1 second and capture 500k incrementing short ints
     fg = gr.flow_graph()
     src = usrp.source_s(fpga_filename = 'usrp_sar.rbf',decim_rate=256)
     src.set_mux(usrp.determine_rx_mux_value(src, (0,0)))
@@ -17,9 +49,21 @@
     fg.connect(src, head, dst)
     fg.run()
 
+def main():
+    parser = OptionParser(option_class=eng_option)
+    parser.add_option("-a", "--amplitude", type="eng_float", default=32000,
+                      help="set amplitude to AMPLITUDE, default is %default", 
metavar="AMPLITUDE")
+    parser.add_option("-f", "--frequency", type="eng_float", default=1e3,
+                      help="set frequency to FREQ in Hz, default is %default", 
metavar="FREQ")
+    parser.add_option("-p", "--phase", type="eng_float", default=0.0,
+                      help="set phase offset to PHASE in radians, default is 
%default", metavar="PHASE")
+    (options, args) = parser.parse_args()
 
-def main():
-    test_transmit()
+    if len(args) != 0:
+        parser.print_help()
+        sys.exit(1)
+
+    test_transmit(options)
     test_receive()
     
 if __name__ == "__main__":