[Commit-gnuradio] r4922 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-04-07 17:37:57 -0600 (Sat, 07 Apr 2007)
New Revision: 4922

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
Log:
now sets up the clock for basic 100 MHz FPGA clock, enough to get going


Modified: gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v   
2007-04-07 23:36:19 UTC (rev 4921)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v   
2007-04-07 23:37:57 UTC (rev 4922)
@@ -31,18 +31,21 @@
    input clk_fpga,           // real 100 MHz FPGA clock
    output [1:0] clk_en,      // controls source of reference clock
    output [1:0] clk_sel,     // controls source of reference clock
-   output clk_func,          // SYNC or reset to 9510
+   input clk_func,          // FIXME needs to be some kind of out SYNC or 
reset to 9510
    input clk_status,         // Monitor PLL or SYNC status
       
    output sen,        // Enable for the AD9510
    output sclk,       // FIXME these need to be shared
-   output sdi,
+   input sdi,
    output sdo
    );
 
    wire   read = 1'b0;    // Always write for now
    wire [1:0] w = 2'b00;  // Always send 1 byte at a time
-   
+   
+       assign clk_sel = 2'b00;  // Both outputs from External Ref (SMA)
+       assign clk_en = 2'b11;   // Both outputs enabled
+       
    reg [20:0]  addr_data;
    //   reg [7:0]   data;
    reg [5:0]   entry;
@@ -53,12 +56,15 @@
    always @*
      case(entry)
        6'd00 : addr_data = {13'h00,8'h10};   // Serial setup
-       6'd01 : addr_data = {13'h0B,8'h00};   // R-Div MSB
-       6'd02 : addr_data = {13'h0C,8'h0A};   // R-Div LSB (R = 10)
-       default : addr_data = {13'h1FFF,8'h00};
+                6'd01 : addr_data = {13'h45,8'h00};   // CLK drives 
distribution
+                6'd02 : addr_data = {13'h3D,8'h80};   // Turn on output 1, 
normal levels
+                6'd03 : addr_data = {13'h4B,8'h80};   // Bypass divider 1 (div 
by 1)
+                6'd04 : addr_data = {13'h5A,8'h01};   // Register Update       
+       default : addr_data = {13'h5A,8'h01};
      endcase // case(entry)
 
-   wire [5:0]  lastentry = 6'd2;
+   wire [5:0]  lastentry = 6'd4;
+   wire done = (counter == 8'd49);
               
    always @(posedge aux_clk)
      if(reset)
@@ -92,7 +98,6 @@
            command <= {command[22:0],1'b0};
        end
 
-   wire done = (counter == 8'd49);
    
    assign sen = (done | counter == 8'd0);  // CSB is high when we're not doing 
anything
    assign sclk = ~counter[0];