[Commit-gnuradio] r4936 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-04-08 22:27:09 -0600 (Sun, 08 Apr 2007)
New Revision: 4936

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
Log:
now locks to an external oscillator if present


Modified: gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v   
2007-04-09 04:24:58 UTC (rev 4935)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v   
2007-04-09 04:27:09 UTC (rev 4936)
@@ -42,9 +42,9 @@
 
    wire   read = 1'b0;    // Always write for now
    wire [1:0] w = 2'b00;  // Always send 1 byte at a time
-   
-       assign clk_sel = 2'b00;  // Both outputs from External Ref (SMA)
-       assign clk_en = 2'b11;   // Both outputs enabled
+   
+       assign clk_sel = 2'b00;  // Both outputs from External Ref (SMA)
+       assign clk_en = 2'b11;   // Both outputs enabled
        
    reg [20:0]  addr_data;
    //   reg [7:0]   data;
@@ -56,14 +56,23 @@
    always @*
      case(entry)
        6'd00 : addr_data = {13'h00,8'h10};   // Serial setup
-                6'd01 : addr_data = {13'h45,8'h00};   // CLK drives 
distribution
-                6'd02 : addr_data = {13'h3D,8'h80};   // Turn on output 1, 
normal levels
-                6'd03 : addr_data = {13'h4B,8'h80};   // Bypass divider 1 (div 
by 1)
-                6'd04 : addr_data = {13'h5A,8'h01};   // Register Update       
-       default : addr_data = {13'h5A,8'h01};
+                6'd01 : addr_data = {13'h45,8'h00};   // CLK2 drives 
distribution, everything on
+                6'd02 : addr_data = {13'h3D,8'h80};   // Turn on output 1, 
normal levels
+                6'd03 : addr_data = {13'h4B,8'h80};   // Bypass divider 1 (div 
by 1)
+                6'd04 : addr_data = {13'h08,8'h47};   // POS PFD, Dig LK Det, 
Charge Pump normal       
+                6'd05 : addr_data = {13'h09,8'h70};   // Max Charge Pump 
current
+                6'd06 : addr_data = {13'h0A,8'h04};   // Normal operation, 
Prescalar Div by 2, PLL On
+                6'd07 : addr_data = {13'h0B,8'h00};   // RDIV MSB (6 bits)
+                6'd08 : addr_data = {13'h0C,8'h01};   // RDIV LSB (8 bits), 
Div by 1
+                6'd09 : addr_data = {13'h0D,8'h00};   // Everything normal, 
Dig Lock Det
+                6'd10 : addr_data = {13'h07,8'h00};    // Disable LOR detect - 
LOR causes failure...
+                6'd11 : addr_data = {13'h04,8'h00};    // A Counter = Don't 
Care
+                6'd12 : addr_data = {13'h05,8'h00};    // B Counter MSB = 0
+                6'd13 : addr_data = {13'h06,8'h05};   // B Counter LSB = 5
+       default : addr_data = {13'h5A,8'h01}; // Register Update
      endcase // case(entry)
 
-   wire [5:0]  lastentry = 6'd4;
+   wire [5:0]  lastentry = 6'd15;
    wire done = (counter == 8'd49);
               
    always @(posedge aux_clk)