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[Commit-gnuradio] r5000 - in gnuradio/branches/developers/matt/u2f: cont
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5000 - in gnuradio/branches/developers/matt/u2f: control_lib top/u2_basic |
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Date: |
Sat, 14 Apr 2007 01:23:44 -0600 (MDT) |
Author: matt
Date: 2007-04-14 01:23:43 -0600 (Sat, 14 Apr 2007)
New Revision: 5000
Added:
gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
gnuradio/branches/developers/matt/u2f/control_lib/wb_sim.v
gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
gnuradio/branches/developers/matt/u2f/top/u2_basic/cmdfile
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_sim_top.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
Log:
wishbone stuff, split toplevel to FPGA and sim-specific
Added: gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -0,0 +1,12 @@
+
+
+module clock_bootstrap_rom(input [15:0] addr, output [47:0] data);
+
+ reg [47:0] rom [0:1023];
+
+ initial
+ $readmemh("bootrom.mem", rom);
+
+ assign data = rom[addr];
+
+endmodule // clock_bootstrap_rom
Modified: gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-04-13 22:15:17 UTC (rev 4999)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -14,102 +14,68 @@
output dsp_clk,
output reset_out,
output wb_clk_o,
- output wb_rst_o);
-
+ output reg wb_rst_o,
+ output reg wb_rst_o_alt,
+
+ output reg start,
+ input done);
+
assign dsp_clk = clk_fpga;
assign reset_out = POR;
- assign wb_rst_o = POR;
- assign wb_clk_o = aux_clk;
-
+ reg started, finished;
-endmodule // system_control
-
-module clock_control
- (input reset,
- input aux_clk, // 25MHz, for before fpga clock is active
- input clk_fpga, // real 100 MHz FPGA clock
- output [1:0] clk_en, // controls source of reference clock
- output [1:0] clk_sel, // controls source of reference clock
- input clk_func, // FIXME needs to be some kind of out SYNC or
reset to 9510
- input clk_status, // Monitor PLL or SYNC status
-
- output sen, // Enable for the AD9510
- output sclk, // FIXME these need to be shared
- input sdi,
- output sdo
- );
-
- wire read = 1'b0; // Always write for now
- wire [1:0] w = 2'b00; // Always send 1 byte at a time
-
- assign clk_sel = 2'b00; // Both outputs from External Ref (SMA)
- assign clk_en = 2'b11; // Both outputs enabled
-
- reg [20:0] addr_data;
- // reg [7:0] data;
- reg [5:0] entry;
- reg start;
- reg [7:0] counter;
- reg [23:0] command;
-
- always @*
- case(entry)
- 6'd00 : addr_data = {13'h00,8'h10}; // Serial setup
- 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives
distribution, everything on
- 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1,
normal levels
- 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div
by 1)
- 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det,
Charge Pump normal
- 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump
current
- 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation,
Prescalar Div by 2, PLL On
- 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits)
- 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits),
Div by 1
- 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal,
Dig Lock Det
- 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect -
LOR causes failure...
- 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't
Care
- 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0
- 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5
- default : addr_data = {13'h5A,8'h01}; // Register Update
- endcase // case(entry)
-
- wire [5:0] lastentry = 6'd15;
- wire done = (counter == 8'd49);
-
- always @(posedge aux_clk)
- if(reset)
+ // Control the resets and start the initial programming of the clocks
+ always @(posedge POR or posedge aux_clk)
+ if(POR)
begin
- entry <= #1 6'd0;
- start <= #1 1'b1;
+ wb_rst_o = 1'b1;
+ finished <= #1 1'b0;
+ start <= #1 1'b0;
+ started <= #1 1'b0;
end
+ else if(wb_rst_o)
+ wb_rst_o <= #1 1'b0;
else if(start)
start <= #1 1'b0;
- else if(done && (entry<lastentry))
+ else if(!started)
begin
- entry <= #1 entry + 6'd1;
+ started <= #1 1'b1;
start <= #1 1'b1;
end
+ else if(done)
+ finished <= #1 1'b1;
+
+ // Control the clocks
+ reg fin_ret_fpga, fin_ret_aux; // Retimed finish signals
+
+ always @(posedge POR or negedge clk_fpga)
+ if(POR)
+ fin_ret_fpga <= #1 1'b0;
+ else
+ fin_ret_fpga <= #1 fin_ret_aux;
+
+ always @(posedge POR or negedge aux_clk)
+ if(POR)
+ fin_ret_aux <= #1 1'b0;
+ else
+ fin_ret_aux <= #1 finished;
- always @(posedge aux_clk)
- if(reset)
- begin
- counter <= #1 7'd0;
- command <= #1 20'd0;
- end
- else if(start)
- begin
- counter <= #1 7'd1;
- command <= #1 {read,w,addr_data};
- end
- else if( |counter && ~done )
- begin
- counter <= #1 counter + 7'd1;
- if(~counter[0])
- command <= {command[22:0],1'b0};
- end
+ assign wb_clk_o = (clk_fpga & fin_ret_fpga) | (aux_clk & ~fin_ret_aux);
+ reg fin_del1, fin_del2, fin_del3;
- assign sen = (done | counter == 8'd0); // CSB is high when we're not doing
anything
- assign sclk = ~counter[0];
- assign sdo = command[23];
+ always @(posedge wb_clk_o)
+ begin
+ fin_del1 <= #1 fin_ret_fpga;
+ fin_del2 <= #1 fin_del1;
+ fin_del3 <= #1 fin_del2;
+ end
+ always @(posedge POR or posedge wb_clk_o)
+ if(POR)
+ wb_rst_o_alt <= #1 1'b1;
+ else if(fin_del3)
+ wb_rst_o_alt <= #1 1'b0;
+
+endmodule // system_control
-endmodule // clock_control
Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -0,0 +1,60 @@
+
+// wb_bus_writer
+//
+// WB Bus Master device to send a sequence of single-word transactions
+// based on a list in a RAM or ROM (FASM interface)
+// ROM data format is {WB_ADDR[15:0],WB_DATA[31:0]}
+// continues until it gets an all-1s entry
+
+module wb_bus_writer (input start,
+ output done,
+ output [15:0] rom_addr,
+ input [47:0] rom_data,
+ // WB Master Interface, don't need wb_dat_i
+ input wb_clk_i,
+ input wb_rst_i,
+ output [31:0] wb_dat_o,
+ input wb_ack_i,
+ output [15:0] wb_adr_o,
+ output wb_cyc_o,
+ output [3:0] wb_sel_o,
+ output wb_stb_o,
+ output wb_we_o
+ );
+
+`define IDLE 0
+`define READ 1
+`define SEND 2
+`define WAIT 3
+
+ reg [3:0] state;
+ reg [15:0] rom_addr;
+
+ wire done = (state != `IDLE) && (&rom_data); // Done
when we see all 1s
+
+ always @(posedge wb_clk_i)
+ if(wb_rst_i)
+ begin
+ rom_addr <= #1 0;
+ state <= #1 0;
+ end
+ else if(start)
+ begin
+ rom_addr <= #1 0;
+ state <= #1 `READ;
+ end
+ else if((state == `READ) && wb_ack_i)
+ if(done)
+ state <= #1 `IDLE;
+ else
+ rom_addr <= #1 rom_addr + 1;
+
+ assign wb_dat_o = rom_data[31:0];
+ assign wb_adr_o = rom_data[47:32];
+ assign wb_sel_o = 4'b1111; // All writes are the full 32 bits
+
+ assign wb_cyc_o = !done & (state != `IDLE);
+ assign wb_stb_o = !done & (state != `IDLE);
+ assign wb_we_o = !done & (state != `IDLE);
+
+endmodule // wb_bus_writer
Modified: gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
2007-04-13 22:15:17 UTC (rev 4999)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -26,7 +26,7 @@
reg [31:0] internal_reg;
- always @(posedge wb_clk)
+ always @(posedge wb_clk_i)
if(wb_rst_i)
internal_reg <= #1 32'b0;
else
Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_sim.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_sim.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_sim.v 2007-04-14
07:23:43 UTC (rev 5000)
@@ -0,0 +1,79 @@
+
+
+module wb_sim();
+
+ wire wb_clk, wb_rst;
+ wire start;
+
+ reg POR, aux_clk, clk_fpga;
+
+ initial POR = 1'b1;
+ initial #103 POR = 1'b0;
+
+ initial aux_clk = 1'b0;
+ always #25 aux_clk = ~aux_clk;
+
+ initial clk_fpga = 1'bx;
+ initial #3007 clk_fpga = 1'b0;
+ always #7 clk_fpga = ~clk_fpga;
+
+ initial begin
+ $dumpfile("wb_sim.vcd");
+ $dumpvars(0,wb_sim);
+ end
+
+ initial #10000 $finish;
+
+ wire [15:0] rom_addr;
+ wire [47:0] rom_data;
+ wire [31:0] wb_dat;
+ wire [15:0] wb_adr;
+ wire wb_cyc,wb_stb,wb_we,wb_ack;
+ wire [3:0] wb_sel;
+
+ wire [31:0] port_output;
+
+
+ system_control system_control(.dsp_clk(dsp_clk),
+ .reset_out(reset_out),
+ .wb_clk_o(wb_clk),
+ .wb_rst_o(wb_rst),
+ .wb_rst_o_alt(wb_rst_o_alt),
+ .start (start),
+ .aux_clk(aux_clk),
+ .clk_fpga(clk_fpga),
+ .POR (POR),
+ .done (done));
+
+ clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
+
+ wb_bus_writer bus_writer(.rom_addr (rom_addr[15:0]),
+ .wb_dat_o (wb_dat[31:0]),
+ .wb_adr_o (wb_adr[15:0]),
+ .wb_cyc_o (wb_cyc),
+ .wb_sel_o (wb_sel[3:0]),
+ .wb_stb_o (wb_stb),
+ .wb_we_o (wb_we),
+ .start (start),
+ .done (done),
+ .rom_data (rom_data[47:0]),
+ .wb_clk_i (wb_clk),
+ .wb_rst_i (wb_rst),
+ .wb_ack_i (wb_ack));
+
+ wb_output_pins32 output_pins(.wb_dat_o(),
+ .wb_ack_o(wb_ack),
+ .port_output(port_output[31:0]),
+ .wb_rst_i(wb_rst),
+ .wb_clk_i(wb_clk),
+ .wb_dat_i(wb_dat[31:0]),
+ .wb_we_i(wb_we),
+ .wb_sel_i(wb_sel[3:0]),
+ .wb_stb_i(wb_stb),
+ .wb_cyc_i(wb_cyc));
+
+
+
+
+endmodule // wb_sim
+
Added: gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
2007-04-14 07:23:43 UTC (rev 5000)
@@ -0,0 +1,21 @@
+// First 16 bits are address, last 32 are data
+// First 4 bits of address select which slave
+0000_0C00_0F03 // Both clk sel choose ext ref (0), both are enabled (1),
turn off SERDES, ADCs, turn on leds
+01 // To SPI
+02 // To I2C
+ffff_ffff_ffff // terminate
+// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives
distribution, everything on
+// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1,
normal levels
+// 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div
by 1)
+// 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det,
Charge Pump normal
+// 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump
current
+// 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation,
Prescalar Div by 2, PLL On
+// 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits)
+// 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits),
Div by 1
+// 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal,
Dig Lock Det
+// 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect -
LOR causes failure...
+// 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't
Care
+// 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0
+// 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5
+ // default : addr_data = {13'h5A,8'h01}; // Register Update
+// @ 55 // Jump to new address 8'h55
Added: gnuradio/branches/developers/matt/u2f/top/u2_basic/cmdfile
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/cmdfile
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/cmdfile 2007-04-14
07:23:43 UTC (rev 5000)
@@ -0,0 +1,8 @@
+-y ../../control_lib
+-y ../../sdr_lib
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/wb_conbus/rtl/verilog
++incdir+../../opencores/wb_conbus/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-13 22:15:17 UTC (rev 4999)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -58,9 +58,10 @@
input RAM_LDn,
// SERDES
- input ser_enable,
- input ser_prbsen,
- input ser_loopen,
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
input ser_tx_clk,
input [15:0] ser_t,
@@ -68,7 +69,6 @@
input ser_tkmsb,
input ser_rx_clk,
- input ser_rx_en,
input [15:0] ser_r,
input ser_rklsb,
input ser_rkmsb,
@@ -76,8 +76,10 @@
// CPLD interface
input spi_cpld_en,
input spi_cpld_dout,
- input spi_cpld_din,
- input spi_cpld_clk, // temporary bootstrap clock
+ input POR,
+ //input spi_cpld_din,
+ input aux_clk, // temporary bootstrap clock
+ //input spi_cpld_clk, // temporary bootstrap clock
// ADC
input [13:0] adc_a,
@@ -156,30 +158,17 @@
);
wire dsp_clk, wb_clk, wb_rst, POR;
- wire aux_clk = spi_cpld_clk;
assign debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
assign debug_clk[0] = aux_clk;
assign debug_clk[1] = clk_fpga;
- clock_control clock_control
- (.reset(reset),
- .aux_clk(aux_clk), // 25MHz, for before fpga clock is active
- .clk_fpga(clk_fpga), // real 100 MHz FPGA clock
- .clk_en(clk_en), // controls source of reference clock
- .clk_sel(clk_sel), // controls source of reference clock
- .clk_func(clk_func), // SYNC or reset to 9510
- .clk_status(clk_status), // Monitor PLL or SYNC status
-
- .sen(sen_clk), // Enable for the AD9510
- .sclk(sclk),.sdi(sdo),.sdo(sdi) // FIXME these need to be shared
- );
-
// 2 Masters
// 0 System controller, to set up AD9510 and clocks
// 1 Main Processor (aeMB)
- // 11+ Slaves
+ // Address bus is 16 bits. Top 4 addr bits select the slave
+ // 11+ Slaves
// 0 Output control lines
// 1 General SPI
// 2 I2C
@@ -193,36 +182,106 @@
// 10 SPI - TXADC
// 11 Interrupt controller?
+`define dw 32
+`define aw 16
+`define sw 4
+
+ wire [`dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
+ wire [`dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o,
s2_dat_i, s3_dat_i,
+ s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o,
s6_dat_i, s7_dat_i;
+ wire [`aw-1:0] m0_adr, m1_adr,
s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
+ wire [`sw-1:0] m0_sel, m1_sel, s0_sel, s1_sel, s2_sel, s3_sel, s4_sel,
s5_sel, s6_sel, s7_sel;
+ wire m0_ack, m1_ack, s0_ack, s1_ack, s2_ack, s3_ack, s4_ack,
s5_ack, s6_ack, s7_ack;
+ wire m0_stb, m1_stb, s0_stb, s1_stb, s2_stb, s3_stb, s4_stb,
s5_stb, s6_stb, s7_stb;
+ wire m0_cyc, m1_cyc, s0_cyc, s1_cyc, s2_cyc, s3_cyc, s4_cyc,
s5_cyc, s6_cyc, s7_cyc;
+ wire m0_err, m1_err, s0_err, s1_err, s2_err, s3_err, s4_err,
s5_err, s6_err, s7_ack;
+ wire m0_rty, m1_rty, s0_rty, s1_rty, s2_rty, s3_rty, s4_rty,
s5_rty, s6_rty, s7_rty;
+ wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we,
s6_we, s7_we;
+ wire m0_cab, m1_cab, s0_cab, s1_cab, s2_cab, s3_cab, s4_cab,
s5_cab, s6_cab, s7_cab;
// Output control lines, organized in 4 8-bit segments -- clock, serdes,
adc, led+misc
+ wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs;
+
+ assign {clk_en[1:0], clk_sel[1:0]} = clock_outs[3:0]; //= { 4'b0,
clk_en[1:0], clk_sel[1:0] };
+ assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} =
serdes_outs[3:0]; // = { 4'b0, ser_enable, ser_prbsen, ser_loopen, ser_rx_en };
+ assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } =
adc_outs[3:0]; // = { 4'b0, adc_oe_a_n, adc_pdn_a, adc_oe_b_n, adc_pdn_b };
+ assign {led2, led1} = misc_outs[1:0]; // = { 6'b0, led2, led1 };
+
wb_output_pins32 control_lines
- (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(),.wb_dat_o(),
- .wb_we_i(),.wb_sel_i(),.wb_stb_i(),.wb_ack_o(),.wb_cyc_i(),
- .port_output({) );
+
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s0_dat_o),.wb_dat_o(s0_dat_i),
+
.wb_we_i(s0_we),.wb_sel_i(s0_sel),.wb_stb_i(s0_stb),.wb_ack_o(s0_ack),.wb_cyc_i(s0_cyc),
+ .port_output( {clock_outs,serdes_outs,adc_outs,misc_outs} ) );
+
+ wire [15:0] rom_addr;
+ wire [47:0] rom_data;
- system_control sysctrl (.aux_clk(aux_clk),.clk_fpga(clk_fpga),.POR(),
+ clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
+
+ wb_bus_writer bus_writer(.rom_addr (rom_addr),
+ .wb_dat_o (m0_dat_i),
+ .wb_adr_o (m0_adr),
+ .wb_cyc_o (m0_cyc),
+ .wb_sel_o (m0_sel),
+ .wb_stb_o (m0_stb),
+ .wb_we_o (m0_we),
+ .start (start),
+ .done (done),
+ .rom_data (rom_data),
+ .wb_clk_i (wb_clk),
+ .wb_rst_i (wb_rst),
+ .wb_ack_i (m0_ack));
+
+ system_control sysctrl (.aux_clk(aux_clk),.clk_fpga(clk_fpga),.POR(POR),
.dsp_clk(dsp_clk),.reset_out(reset),
- .wb_clk_o(wb_clk),.wb_rst_o(wb_rst));
+ .wb_clk_o(wb_clk),.wb_rst_o(wb_rst),.wb_rst_o_alt(),
+ .start(start),.done(done) );
- i2c_master_top i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(),
- .wb_adr_i(),.wb_dat_i(),.wb_dat_o(),
- .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),
- .wb_ack_o(),.wb_inta_o(),
- .scl_pad_i(),.scl_pad_o(),.scl_padoen_o(),
- .sda_pad_i(),.sda_pad_o(),.sda_padoen_o() );
-
spi_top shared_spi
-
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
- .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),.wb_ack_o(),.wb_err_o(),.wb_int_o(),
+
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),.wb_dat_o(s1_dat_i),
+
.wb_sel_i(s1_sel),.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_cyc_i(s1_cyc),.wb_ack_o(s1_ack),
+ .wb_err_o(s1_err),.wb_int_o(s1_int),
.ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
-`define dw 32
-`define aw 16
-`define sw 4
+ i2c_master_top i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(),
+
.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
+ .wb_we_i(s2_we),.wb_stb_i(s2_stb),.wb_cyc_i(s2_cyc),
+ .wb_ack_o(s2_ack),.wb_inta_o(st_int),
+
.scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+
.sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+ assign m1_cyc=1'b0;
- wb_conbus_top wb_conbus_top(/*AUTOINST*/);
+ wb_conbus_top #(.s0_addr_w(4),.s0_addr(4'h0),.s1_addr_w(4),.s1_addr(4'h1),
+ .s27_addr_w(4),.s2_addr(4'h2),.s3_addr(4'h3),.s4_addr(4'h4),
+ .s5_addr(4'h5),.s6_addr(4'h6),.s7_addr(4'h7),
+ .dw(`dw),.aw(`aw),.sw(`sw)) wb_conbus_top
+ (.clk_i(wb_clk),.rst_i(wb_rst),
+
+
.m0_dat_o(m0_dat_o),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_i),
+
.m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),.m0_cab_i(m0_cab),
+
.m1_dat_o(m1_dat_o),.m1_ack_o(m1_ack),.m1_err_o(m1_err),.m1_rty_o(m1_rty),.m1_dat_i(m1_dat_i),
+
.m1_adr_i(m1_adr),.m1_sel_i(m1_sel),.m1_we_i(m1_we),.m1_cyc_i(m1_cyc),.m1_stb_i(m1_stb),.m1_cab_i(m1_cab),
+
+
.m2_cyc_i(1'b0),.m3_cyc_i(1'b0),.m4_cyc_i(1'b0),.m5_cyc_i(1'b0),.m6_cyc_i(1'b0),.m7_cyc_i(1'b0),
+ .s0_dat_o(s0_dat_o),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o
(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
+
.s0_cab_o(s0_cab),.s0_dat_i(s0_dat_i),.s0_ack_i(s0_ack),.s0_err_i(s0_err),.s0_rty_i(s0_rty),
+ .s1_dat_o(s1_dat_o),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o
(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
+
.s1_cab_o(s1_cab),.s1_dat_i(s1_dat_i),.s1_ack_i(s1_ack),.s1_err_i(s1_err),.s1_rty_i(s1_rty),
+ .s2_dat_o(s2_dat_o),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o
(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
+
.s2_cab_o(s2_cab),.s2_dat_i(s2_dat_i),.s2_ack_i(s2_ack),.s2_err_i(s2_err),.s2_rty_i(s2_rty),
+ .s3_dat_o(s3_dat_o),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o
(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
+
.s3_cab_o(s3_cab),.s3_dat_i(s3_dat_i),.s3_ack_i(s3_ack),.s3_err_i(s3_err),.s3_rty_i(s3_rty),
+ .s4_dat_o(s4_dat_o),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o
(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
+
.s4_cab_o(s4_cab),.s4_dat_i(s4_dat_i),.s4_ack_i(s4_ack),.s4_err_i(s4_err),.s4_rty_i(s4_rty),
+ .s5_dat_o(s5_dat_o),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o
(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
+
.s5_cab_o(s5_cab),.s5_dat_i(s5_dat_i),.s5_ack_i(s5_ack),.s5_err_i(s5_err),.s5_rty_i(s5_rty),
+ .s6_dat_o(s6_dat_o),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o
(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
+
.s6_cab_o(s6_cab),.s6_dat_i(s6_dat_i),.s6_ack_i(s6_ack),.s6_err_i(s6_err),.s6_rty_i(s6_rty),
+ .s7_dat_o(s7_dat_o),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o
(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
+
.s7_cab_o(s7_cab),.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
+ );
+
-
endmodule // u2_basic
// Local Variables:
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
2007-04-13 22:15:17 UTC (rev 4999)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -60,9 +60,10 @@
input RAM_LDn,
// SERDES
- input ser_enable,
- input ser_prbsen,
- input ser_loopen,
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
input ser_tx_clk,
input [15:0] ser_t,
@@ -70,7 +71,6 @@
input ser_tkmsb,
input ser_rx_clk,
- input ser_rx_en,
input [15:0] ser_r,
input ser_rklsb,
input ser_rkmsb,
@@ -78,7 +78,7 @@
// CPLD interface
input spi_cpld_en,
input spi_cpld_dout,
- input spi_cpld_din,
+ input spi_cpld_din, // temporary POR
input spi_cpld_clk, // temporary bootstrap clock
// ADC
@@ -175,11 +175,15 @@
// Don't use external transistors for open drain, the FPGA implements this
assign SCL_force = 1'b0;
assign SDA_force = 1'b0;
+
+ // LEDs are active low outputs
+ assign led1 = ~led1_int;
+ assign led2 = ~led2_int;
u2_basic u2_basic(/*AUTOINST*/
// Outputs
- .led1 (led1),
- .led2 (led2),
+ .led1 (led1_int),
+ .led2 (led2_int),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
.exp_pps_out (exp_pps_out),
@@ -238,8 +242,10 @@
.ser_rkmsb (ser_rkmsb),
.spi_cpld_en (spi_cpld_en),
.spi_cpld_dout (spi_cpld_dout),
- .spi_cpld_din (spi_cpld_din),
- .spi_cpld_clk (spi_cpld_clk),
+ .POR (spi_cpld_din), // FIXME
+ .aux_clk (spi_cpld_clk), // FIXME
+ // .spi_cpld_din (spi_cpld_din), // FIXME
+ // .spi_cpld_clk (spi_cpld_clk), // FIXME
.adc_a (adc_a[13:0]),
.adc_ovf_a (adc_ovf_a),
.adc_b (adc_b[13:0]),
Added: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_sim_top.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_sim_top.v
2007-04-14 07:23:43 UTC (rev 5000)
@@ -0,0 +1,286 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: safe_bringup
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module u2_sim_top();
+
+ // Misc, debug
+ wire led1;
+ wire led2;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ // Expansion
+ wire exp_pps_in;
+ wire exp_pps_out;
+
+ // GMII
+ // GMII-CTRL
+ wire GMII_COL;
+ wire GMII_CRS;
+
+ // GMII-TX
+ wire [7:0] GMII_TXD;
+ wire GMII_TX_EN;
+ wire GMII_TX_ER;
+ wire GMII_GTX_CLK;
+ wire GMII_TX_CLK; // 100mbps clk
+
+ // GMII-RX
+ wire [7:0] GMII_RXD;
+ wire GMII_RX_CLK;
+ wire GMII_RX_DV;
+ wire GMII_RX_ER;
+
+ // GMII-Management
+ wire MDIO;
+ wire MDC;
+ wire PHY_INTn; // open drain
+ wire PHY_RESETn;
+ wire PHY_CLK; // possibly use on-board osc
+
+ // RAM
+ wire [17:0] RAM_D;
+ wire [18:0] RAM_A;
+ wire RAM_CE1n;
+ wire RAM_CENn;
+ wire RAM_CLK;
+ wire RAM_WEn;
+ wire RAM_OEn;
+ wire RAM_LDn;
+
+ // SERDES
+ wire ser_enable;
+ wire ser_prbsen;
+ wire ser_loopen;
+
+ wire ser_tx_clk;
+ wire [15:0] ser_t;
+ wire ser_tklsb;
+ wire ser_tkmsb;
+
+ wire ser_rx_clk;
+ wire ser_rx_en;
+ wire [15:0] ser_r;
+ wire ser_rklsb;
+ wire ser_rkmsb;
+
+ // CPLD interface
+ wire spi_cpld_en;
+ wire spi_cpld_dout;
+ wire spi_cpld_din;
+ wire spi_cpld_clk; // temporary bootstrap clock
+
+ // ADC
+ wire [13:0] adc_a;
+ wire adc_ovf_a;
+ wire adc_oen_a;
+ wire adc_pdn_a;
+
+ wire [13:0] adc_b;
+ wire adc_ovf_b;
+ wire adc_oen_b;
+ wire adc_pdn_b;
+
+ // DAC
+ wire [15:0] dac_a;
+ wire [15:0] dac_b;
+
+
+ // I2C
+ wire SCL;
+ wire SDA;
+
+ // Clock Gen Control
+ wire [1:0] clk_en;
+ wire [1:0] clk_sel;
+ wire clk_func; // FIXME is an input to control the 9510
+ wire clk_status;
+
+ // Clocks
+ reg clk_fpga;
+ wire clk_to_mac;
+ wire pps_in;
+
+ // Generic SPI
+ wire sclk;
+ wire sen_clk;
+ wire sen_dac;
+ wire sdi;
+ wire sdo;
+
+ // TX DBoard
+ wire sen_tx_db;
+ wire sclk_tx_db;
+ wire sdo_tx_db;
+ wire sdi_tx_db;
+
+ wire sen_tx_adc;
+ wire sclk_tx_adc;
+ wire sdo_tx_adc;
+ wire sdi_tx_adc;
+
+ wire sen_tx_dac;
+ wire sclk_tx_dac;
+ wire sdi_tx_dac;
+
+ wire [15:0] io_tx;
+
+ // RX DBoard
+ wire sen_rx_db;
+ wire sclk_rx_db;
+ wire sdo_rx_db;
+ wire sdi_rx_db;
+
+ wire sen_rx_adc;
+ wire sclk_rx_adc;
+ wire sdo_rx_adc;
+ wire sdi_rx_adc;
+
+ wire sen_rx_dac;
+ wire sclk_rx_dac;
+ wire sdi_rx_dac;
+
+ wire [15:0] io_rx;
+
+ wire wb_clk, wb_rst;
+ wire start;
+
+ reg POR, aux_clk;
+
+ initial POR = 1'b1;
+ initial #103 POR = 1'b0;
+
+ initial aux_clk = 1'b0;
+ always #25 aux_clk = ~aux_clk;
+
+ initial clk_fpga = 1'bx;
+ initial #3007 clk_fpga = 1'b0;
+ always #7 clk_fpga = ~clk_fpga;
+
+ initial begin
+ $dumpfile("u2_sim_top.vcd");
+ $dumpvars(0,u2_sim_top);
+ end
+
+ initial #10000 $finish;
+
+ u2_basic u2_basic(/*AUTOINST*/
+ // Outputs
+ .led1 (led1),
+ .led2 (led2),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_out (exp_pps_out),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .sclk (sclk),
+ .sen_clk (sen_clk),
+ .sdi (sdi),
+ // Inputs
+ .exp_pps_in (exp_pps_in),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .RAM_D (RAM_D[17:0]),
+ .RAM_A (RAM_A[18:0]),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_rx_en (ser_rx_en),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .spi_cpld_en (spi_cpld_en),
+ .spi_cpld_dout (spi_cpld_dout),
+ //.spi_cpld_din (spi_cpld_din),
+ //.spi_cpld_clk (spi_cpld_clk),
+ .POR (POR), // FIXME
+ .aux_clk (aux_clk), // FIXME
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .scl_pad_i (scl_pad_i),
+ .sda_pad_i (sda_pad_i),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .clk_fpga (clk_fpga),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .sen_dac (sen_dac),
+ .sdo (sdo),
+ .sen_tx_db (sen_tx_db),
+ .sclk_tx_db (sclk_tx_db),
+ .sdo_tx_db (sdo_tx_db),
+ .sdi_tx_db (sdi_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sclk_tx_adc (sclk_tx_adc),
+ .sdo_tx_adc (sdo_tx_adc),
+ .sdi_tx_adc (sdi_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sclk_tx_dac (sclk_tx_dac),
+ .sdi_tx_dac (sdi_tx_dac),
+ .io_tx (io_tx[15:0]),
+ .sen_rx_db (sen_rx_db),
+ .sclk_rx_db (sclk_rx_db),
+ .sdo_rx_db (sdo_rx_db),
+ .sdi_rx_db (sdi_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sclk_rx_adc (sclk_rx_adc),
+ .sdo_rx_adc (sdo_rx_adc),
+ .sdi_rx_adc (sdi_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .sclk_rx_dac (sclk_rx_dac),
+ .sdi_rx_dac (sdi_rx_dac),
+ .io_rx (io_rx[15:0]));
+
+endmodule // u2_sim_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+//
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
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