[Commit-gnuradio] r5003 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/lib fpga/rbf fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python

[jcorgan]

Author: jcorgan
Date: 2007-04-15 13:50:09 -0600 (Sun, 15 Apr 2007)
New Revision: 5003

Added:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar_max.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar_max.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
Modified:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/cordic_nco.v
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/Makefile.am
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
Log:
Work in progress.  Conditionalized build for either 32 MHz or 64 MHz tx clock, 
cleaned up enable logic.

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/cordic_nco.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/cordic_nco.v 
    2007-04-15 15:52:13 UTC (rev 5002)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/cordic_nco.v 
    2007-04-15 19:50:09 UTC (rev 5003)
@@ -34,6 +34,7 @@
 
    reg [31:0] phase_reg;
    wire [31:0] phase = phase_reg + phs_i;
+   wire [15:0] mag;
    
    always @(posedge clk_i)
      begin
@@ -43,9 +44,11 @@
          phase_reg <= phase_reg + freq_i;
      end
 
+   assign mag = ena_i ? mag_i : 16'b0;
+
    cordic tx_cordic
-     (.clock(clk_i),.reset(rst_in),.enable(ena_i&strobe_i), 
-       .xi(mag_i),.yi(16'b0),.zi(phase[31:16]),
+     (.clock(clk_i),.reset(rst_in),.enable(strobe_i), 
+       .xi(mag),.yi(16'b0),.zi(phase[31:16]),
        .xo(data_i_o),.yo(data_q_o),.zo());
          
 endmodule // cordic_nco

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
  2007-04-15 15:52:13 UTC (rev 5002)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
  2007-04-15 19:50:09 UTC (rev 5003)
@@ -19,17 +19,21 @@
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
 
-module dac_interface(clk_i,rst_i,ena_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
+`include "../toplevel/config.vh"
+
+module 
dac_interface(clk_i,rst_i,ena_i,strobe_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
    input clk_i;
    input rst_i;
    input ena_i;
-
+   input strobe_i;
+   
    input [15:0] tx_i_i;
    input [15:0] tx_q_i;
 
    output [15:0] tx_data_o;
    output       tx_sync_o;
 
+`ifdef TX_RATE_MAX
    wire clk128;
    reg clk64_d;
    reg [15:0] tx_data_o;
@@ -39,17 +43,18 @@
 
    // Register the clk64 clock in the clk128 domain
    always @(posedge clk128)
-     begin
-       if (rst_i | ~ena_i)
-         clk64_d <= 1'b0;
-       else
-         clk64_d <= clk_i;
-     end
+     clk64_d <= clk_i;
 
-   assign tx_sync_o = clk64_d;
-   
    // Register the tx data in the clk128 domain
    always @(posedge clk128)
-         tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
+     tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
 
+   assign tx_sync_o = clk64_d;
+   
+
+`else // !`ifdef TX_RATE_MAX
+   assign tx_data_o = strobe_i ? tx_i_i : tx_q_i;
+   assign tx_sync_o = strobe_i;
+`endif // !`ifdef TX_RATE_MAX
+   
 endmodule // dac_interface

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v 
2007-04-15 15:52:13 UTC (rev 5002)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/sar_tx.v 
2007-04-15 19:50:09 UTC (rev 5003)
@@ -41,15 +41,10 @@
    setting_reg #(`FR_USER_1) 
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq));
    setting_reg #(`FR_USER_2) 
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phase));
    
-   wire [15:0]          data_i_o;
-   wire [15:0]          data_q_o;
-   
    cordic_nco 
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
                  .mag_i(mag[15:0]),.freq_i(freq),.phs_i(phase),
-                 .data_i_o(data_i_o),.data_q_o(data_q_o));
+                 .data_i_o(tx_i_o),.data_q_o(tx_q_o));
 
-   assign tx_i_o = ena_i ? data_i_o : 16'b0;
-   assign tx_q_o = ena_i ? data_q_o : 16'b0;
    assign debug_o = 16'hAA55;
          
 endmodule // sar_tx

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/Makefile.am
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/Makefile.am  
    2007-04-15 15:52:13 UTC (rev 5002)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/Makefile.am  
    2007-04-15 19:50:09 UTC (rev 5003)
@@ -24,7 +24,9 @@
 datadir = $(prefix)/share/usrp
 
 rbfs =         rev2/usrp_sar.rbf \
-       rev4/usrp_sar.rbf
+       rev2/usrp_sar_max.rbf \
+       rev4/usrp_sar.rbf \
+       rev4/usrp_sar_max.rbf
 
 
 EXTRA_DIST = \

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
===================================================================
(Binary files differ)

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar_max.rbf
===================================================================
(Binary files differ)


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar_max.rbf
___________________________________________________________________
Name: svn:executable
   + *
Name: svn:mime-type
   + application/octet-stream

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
===================================================================
(Binary files differ)

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar_max.rbf
===================================================================
(Binary files differ)


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar_max.rbf
___________________________________________________________________
Name: svn:executable
   + *
Name: svn:mime-type
   + application/octet-stream

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
                           (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
   2007-04-15 19:50:09 UTC (rev 5003)
@@ -0,0 +1,24 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// Uncomment to enable 64 MHz Tx clock, otherwise 32 MHz
+//`define TX_RATE_MAX
+


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/config.vh
___________________________________________________________________
Name: svn:executable
   + *

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
    2007-04-15 15:52:13 UTC (rev 5002)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
    2007-04-15 19:50:09 UTC (rev 5003)
@@ -91,7 +91,7 @@
                altpll_component.clk0_divide_by = 1,
                altpll_component.clk0_duty_cycle = 50,
                altpll_component.clk0_multiply_by = 2,
-               altpll_component.clk0_phase_shift = "3000",
+               altpll_component.clk0_phase_shift = "0000",
                altpll_component.compensate_clock = "CLK0",
                altpll_component.inclk0_input_frequency = 15625,
                altpll_component.intended_device_family = "Cyclone",

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-15 15:52:13 UTC (rev 5002)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-15 19:50:09 UTC (rev 5003)
@@ -20,8 +20,7 @@
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
 
-`include "../../../../usrp/firmware/include/fpga_regs_common.v"
-`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
+`include "config.vh"
 
 module usrp_sar
 (output MYSTERY_SIGNAL,
@@ -110,13 +109,20 @@
    wire [15:0] tx_data;
    wire [15:0] tx_debug;
 
-   // Transmitter creates a new output sample per clk64
-   sar_tx 
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(1'b1),
+   wire        sar_tx_strobe;
+`ifdef TX_RATE_MAX
+   assign      sar_tx_strobe = 1'b1;
+`else
+   assign      sar_tx_strobe = tx_sample_strobe; // Generated by 
master_control, every other clock
+`endif
+
+   // Transmitter creates a new output sample per sar_tx_strobe
+   sar_tx 
transmitter(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(sar_tx_strobe),
                      
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
                      .tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
 
 
-   dac_interface 
dac_interface(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),
+   dac_interface 
dac_interface(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),.strobe_i(sar_tx_strobe),
                               
.tx_i_i(tx_i),.tx_q_i(tx_q),.tx_data_o(tx_data),.tx_sync_o(TXSYNC_A));
 
    assign tx_a = tx_data[15:2];

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py  
2007-04-15 15:52:13 UTC (rev 5002)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py  
2007-04-15 19:50:09 UTC (rev 5003)
@@ -6,20 +6,31 @@
 from optparse import OptionParser
 import math
 
+# Set to 0 for 32 MHz tx clock, 1 for 64 MHz tx clock
+# Must match config.vh in FPGA code
+TX_RATE_MAX = 0
+_tx_freq_divisor = 32e6*(TX_RATE_MAX+1)
+
 class sar_tx:
     def __init__(self):
-       self.trans = usrp.sink_s(fpga_filename='usrp_sar.rbf')
-        self.set_tx_intfc(0x09)
-        self.set_tx_dig(0x11)
-       self.set_tx_dll(0x49)
-        self.set_tx_clkout(0x00)
+       if TX_RATE_MAX == 1:
+           fname = 'usrp_sar_max.rbf'
+       else:
+           fname = 'usrp_sar.rbf'
+       print "Using FPGA bitstream", fname
+       self.trans = usrp.sink_s(fpga_filename=fname)
+       if TX_RATE_MAX == 1:
+           self.set_tx_intfc(0x09)
+           self.set_tx_dig(0x11)
+           self.set_tx_dll(0x49)
+           self.set_tx_clkout(0x00)
        self.set_amplitude(32000)
         
     def set_amplitude(self, amplitude):
        self.trans._write_fpga_reg(usrp.FR_USER_0, int(amplitude))
 
     def tune(self, freq):
-       ftw = int(freq*(2**32)/64e6)
+       ftw = int(freq*(2**32)/_tx_freq_divisor)
        self.trans._write_fpga_reg(usrp.FR_USER_1, ftw)
 
     def set_phase(self, phase):
@@ -91,7 +102,7 @@
         sys.exit(1)
 
     test_transmit(options)
-    test_receive()
+    #test_receive()
     
 if __name__ == "__main__":
     main()