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[Commit-gnuradio] r5027 - in gnuradio/branches/developers/matt/u2f/top:
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5027 - in gnuradio/branches/developers/matt/u2f/top: . u2_basic u2_fpga |
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Date: |
Mon, 16 Apr 2007 16:26:02 -0600 (MDT) |
Author: matt
Date: 2007-04-16 16:26:02 -0600 (Mon, 16 Apr 2007)
New Revision: 5027
Added:
gnuradio/branches/developers/matt/u2f/top/u2_fpga/
gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
Removed:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
move stuff around
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
2007-04-16 21:39:25 UTC (rev 5026)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/bootrom.mem
2007-04-16 22:26:02 UTC (rev 5027)
@@ -1,8 +1,11 @@
// First 16 bits are address, last 32 are data
// First 4 bits of address select which slave
-0000_0C00_0F03 // Both clk sel choose ext ref (0), both are enabled (1),
turn off SERDES, ADCs, turn on leds
-01 // To SPI
-02 // To I2C
+0000_0C00_0F03 // Both clk sel choose ext ref (0), both are enabled (1),
turn off SERDES, ADCs, turn on leds
+1014_0000_0000 // SPI: Set Divider to div by 2
+1018_0000_0001 // SPI: Choose AD9510
+1010_0000_3418 // SPI: Auto-slave select, interrupt when done, TX_NEG,
24-bit word
+1000_0000_0010 // SPI: AD9510 A:0 D:10 Set up AD9510 SPI
+1010_0000_3518 // SPI: SEND IT Auto-slave select, interrupt when done,
TX_NEG, 24-bit word
ffff_ffff_ffff // terminate
// 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives
distribution, everything on
// 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1,
normal levels
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-16 21:39:25 UTC (rev 5026)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-16 22:26:02 UTC (rev 5027)
@@ -240,7 +240,7 @@
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s1_adr),.wb_dat_i(s1_dat_o),.wb_dat_o(s1_dat_i),
.wb_sel_i(s1_sel),.wb_we_i(s1_we),.wb_stb_i(s1_stb),.wb_cyc_i(s1_cyc),.wb_ack_o(s1_ack),
.wb_err_o(s1_err),.wb_int_o(s1_int),
- .ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
+
.ss_pad_o({sen_dac,sen_clk}),.sclk_pad_o(sclk),.mosi_pad_o(),.miso_pad_i() );
i2c_master_top i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(),
.wb_adr_i(s2_adr),.wb_dat_i(s2_dat_o),.wb_dat_o(s2_dat_i),
@@ -281,6 +281,11 @@
.s7_cab_o(s7_cab),.s7_dat_i(s7_dat_i),.s7_ack_i(s7_ack),.s7_err_i(s7_err),.s7_rty_i(s7_rty)
);
+ assign s3_ack = 1'b0;
+ assign s4_ack = 1'b0;
+ assign s5_ack = 1'b0;
+ assign s6_ack = 1'b0;
+ assign s7_ack = 1'b0;
endmodule // u2_basic
Deleted: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
Copied: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v (from
rev 5000, gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v)
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.v
2007-04-16 22:26:02 UTC (rev 5027)
@@ -0,0 +1,293 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: safe_bringup
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module u2_fpga_top
+ (
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ input [7:0] GMII_TXD,
+ input GMII_TX_EN,
+ input GMII_TX_ER,
+ input GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ input MDIO,
+ input MDC,
+ input PHY_INTn, // open drain
+ input PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ input [17:0] RAM_D,
+ input [18:0] RAM_A,
+ input RAM_CE1n,
+ input RAM_CENn,
+ input RAM_CLK,
+ input RAM_WEn,
+ input RAM_OEn,
+ input RAM_LDn,
+
+ // SERDES
+ output ser_enable,
+ output ser_prbsen,
+ output ser_loopen,
+ output ser_rx_en,
+
+ input ser_tx_clk,
+ input [15:0] ser_t,
+ input ser_tklsb,
+ input ser_tkmsb,
+
+ input ser_rx_clk,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ input spi_cpld_en,
+ input spi_cpld_dout,
+ input spi_cpld_din, // temporary POR
+ input spi_cpld_clk, // temporary bootstrap clock
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+
+ // I2C
+ inout SCL,
+ inout SDA,
+ output SCL_force,
+ output SDA_force,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p,
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ input sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ input sen_tx_db,
+ input sclk_tx_db,
+ input sdo_tx_db,
+ input sdi_tx_db,
+
+ input sen_tx_adc,
+ input sclk_tx_adc,
+ input sdo_tx_adc,
+ input sdi_tx_adc,
+
+ input sen_tx_dac,
+ input sclk_tx_dac,
+ input sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ input sen_rx_db,
+ input sclk_rx_db,
+ input sdo_rx_db,
+ input sdi_rx_db,
+
+ input sen_rx_adc,
+ input sclk_rx_adc,
+ input sdo_rx_adc,
+ input sdi_rx_adc,
+
+ input sen_rx_dac,
+ input sclk_rx_dac,
+ input sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ wire clk_fpga;
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFGDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
+
+ // Don't use external transistors for open drain, the FPGA implements this
+ assign SCL_force = 1'b0;
+ assign SDA_force = 1'b0;
+
+ // LEDs are active low outputs
+ assign led1 = ~led1_int;
+ assign led2 = ~led2_int;
+
+ u2_basic u2_basic(/*AUTOINST*/
+ // Outputs
+ .led1 (led1_int),
+ .led2 (led2_int),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_out (exp_pps_out),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .sclk (sclk),
+ .sen_clk (sen_clk),
+ .sdi (sdi),
+ // Inputs
+ .exp_pps_in (exp_pps_in),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .RAM_D (RAM_D[17:0]),
+ .RAM_A (RAM_A[18:0]),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_rx_en (ser_rx_en),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .spi_cpld_en (spi_cpld_en),
+ .spi_cpld_dout (spi_cpld_dout),
+ .POR (spi_cpld_din), // FIXME
+ .aux_clk (spi_cpld_clk), // FIXME
+ // .spi_cpld_din (spi_cpld_din), // FIXME
+ // .spi_cpld_clk (spi_cpld_clk), // FIXME
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .scl_pad_i (scl_pad_i),
+ .sda_pad_i (sda_pad_i),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .clk_fpga (clk_fpga),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .sen_dac (sen_dac),
+ .sdo (sdo),
+ .sen_tx_db (sen_tx_db),
+ .sclk_tx_db (sclk_tx_db),
+ .sdo_tx_db (sdo_tx_db),
+ .sdi_tx_db (sdi_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sclk_tx_adc (sclk_tx_adc),
+ .sdo_tx_adc (sdo_tx_adc),
+ .sdi_tx_adc (sdi_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sclk_tx_dac (sclk_tx_dac),
+ .sdi_tx_dac (sdi_tx_dac),
+ .io_tx (io_tx[15:0]),
+ .sen_rx_db (sen_rx_db),
+ .sclk_rx_db (sclk_rx_db),
+ .sdo_rx_db (sdo_rx_db),
+ .sdi_rx_db (sdi_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sclk_rx_adc (sclk_rx_adc),
+ .sdo_rx_adc (sdo_rx_adc),
+ .sdi_rx_adc (sdi_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .sclk_rx_dac (sclk_rx_dac),
+ .sdi_rx_dac (sdi_rx_dac),
+ .io_rx (io_rx[15:0]));
+
+endmodule // u2_fpga_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+//
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
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matt <=