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[Commit-gnuradio] r5051 - in gnuradio/branches/developers/thottelt: . in
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From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5051 - in gnuradio/branches/developers/thottelt: . inband/usrp/fpga/sdr_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations tx_data |
|
Date: |
Fri, 20 Apr 2007 13:39:09 -0600 (MDT) |
Author: thottelt
Date: 2007-04-20 13:39:09 -0600 (Fri, 20 Apr 2007)
New Revision: 5051
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
gnuradio/branches/developers/thottelt/simulations/
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
Log:
moved code from modelsim to quartus
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,146 @@
+module chan_fifo_reader
+ ( input reset,
+ input tx_clock,
+ input [31:0]adc_clock,
+ input [15:0]data_bus,
+ input WR,
+ input pkt_complete,
+ output reg [15:0]tx_q,
+ output reg [15:0]tx_i,
+ output reg overrun,
+ output reg underrun) ;
+
+ // States
+ `define IDLE 4'd0
+ `define READ 4'd1
+ `define HEADER1 4'd2
+ `define HEADER2 4'd3
+ `define TIMESTAMP1 4'd4
+ `define TIMESTAMP2 4'd5
+ `define WAIT 4'd6
+ `define SENDWAIT 4'd7
+ `define SEND 4'd8
+ `define DISCARD 4'd9
+
+ // fifo inputs
+ reg skip;
+ reg rdreq;
+
+ // fifo ouputs
+ wire [15:0] fifodata;
+ wire pkt_waiting;
+
+ // Channel fifo
+ data_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(tx_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip)
+ );
+
+ // State registers
+ reg[3:0] reader_state;
+ reg[3:0] reader_next_state;
+
+ //Variables
+ reg[8:0] payload_len;
+ reg[8:0] read_len;
+ reg[31:0] timestamp;
+ reg burst;
+
+ always @(posedge tx_clock)
+ begin
+ if (reset) begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ overrun <= 0;
+ underrun <= 0;
+ burst <= 0;
+ end
+ else begin
+ reader_state = reader_next_state;
+ case (reader_state)
+ `IDLE: begin
+ reader_next_state <= pkt_waiting ? `READ : `IDLE;
+ rdreq <= pkt_waiting;
+ end
+ `READ: begin
+ reader_next_state <= `HEADER1;
+ end
+ `HEADER1: begin
+ reader_next_state <= `HEADER2;
+ end
+ `HEADER2: begin
+ payload_len <= (fifodata & 16'h1FF);
+ read_len <= 9'd0;
+ reader_next_state <= `TIMESTAMP1;
+ end
+ `TIMESTAMP1: begin
+ timestamp <= {fifodata, 16'b0};
+ rdreq <= 0;
+ reader_next_state <= `TIMESTAMP2;
+ end
+ `TIMESTAMP2: begin
+ timestamp <= timestamp + fifodata;
+ reader_next_state <= `WAIT;
+ end
+ `WAIT: begin
+ // Wait a little bit more
+ if (timestamp > adc_clock + 5) begin
+ reader_next_state <= `WAIT;
+ end
+ // Prepare to send
+ else if (timestamp < adc_clock + 5
+ && timestamp > adc_clock) begin
+ reader_next_state <= `SENDWAIT;
+ rdreq <= 1;
+ end
+ // Outdated
+ else if (timestamp < adc_clock) begin
+ reader_next_state <= `DISCARD;
+ skip <= 1;
+ end
+ end
+
+ `SENDWAIT: begin
+ reader_next_state <= `SEND;
+ end
+
+ `SEND: begin
+ read_len <= read_len + 2;
+
+ // If end of payload...
+ if (read_len == payload_len) begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < 508);
+ end
+ else begin
+ if (read_len == payload_len - 4)
+ rdreq <= 0;
+ // Forward data
+ tx_q <= fifodata;
+ end
+ end
+ `DISCARD: begin
+ skip <= 0;
+ reader_next_state <= `IDLE;
+ end
+
+ default: begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
2007-04-19 19:50:06 UTC (rev 5050)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/tx_buffer.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -32,10 +32,11 @@
output wire have_space,
output reg tx_underrun,
input wire [3:0] channels,
- output reg [15:0] tx_i_0,
- output reg [15:0] tx_q_0,
- output reg [15:0] tx_i_1,
- output reg [15:0] tx_q_1,
+ output [15:0] tx_i_0,
+ output [15:0] tx_q_0,
+ output [15:0] tx_i_1,
+ output [15:0] tx_q_1,
+ //NOT USED
output reg [15:0] tx_i_2,
output reg [15:0] tx_q_2,
output reg [15:0] tx_i_3,
@@ -46,8 +47,67 @@
output wire tx_empty,
output [11:0] debugbus
);
+
+ wire [15:0] tx_data_bus;
+ //TODO: increment it
+ reg [31:0] time_counter;
+
+ wire WR_chan_0;
+ wire chan_0_done;
+ wire OR0;
+ wire UR0;
- wire [11:0] txfifolevel;
+ wire WR_chan_1;
+ wire chan_1_done;
+ wire OR1;
+ wire UR1;
+
+ // NOT USED yet
+ wire WR_cmd;
+ wire cmd_done;
+
+ usb_fifo_reader usb_reader (
+ .reset(reset),
+ .usb_clock(usbclk),
+ .WR(WR),
+ .tx_clock(txclk),
+ .tx_data_bus(tx_data_bus),
+ .WR_chan_0(WR_chan_0),
+ .WR_chan_1(WR_chan_1),
+ .WR_cmd(WR_cmd),
+ .chan_0_done(chan_0_done),
+ .chan_1_done(chan_1_done),
+ .cmd_done(cmd_done),
+ .usb_data(usbdata)
+ );
+
+ chan_fifo_reader chan_0_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_0),
+ .pkt_complete(chan_0_done),
+ .tx_q(tx_q_0),
+ .tx_i(tx_i_0),
+ .overrun(OR0),
+ .underrun(UR0)
+ );
+
+ chan_fifo_reader chan_1_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_1),
+ .pkt_complete(chan_1_done),
+ .tx_q(tx_q_1),
+ .tx_i(tx_i_1),
+ .overrun(OR1),
+ .underrun(UR1)
+ );
+
+ /*wire [11:0] txfifolevel;
reg [8:0] write_count;
wire tx_full;
wire [15:0] fifodata;
@@ -132,7 +192,7 @@
assign debugbus[5] = write_count[8];
assign debugbus[6] = txstrobe;
assign debugbus[7] = rdreq;
- assign debugbus[11:8] = load_next;
+ assign debugbus[11:8] = load_next;*/
endmodule // tx_buffer
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,153 @@
+module usb_fifo_reader (
+ input usb_clock,
+ input tx_clock,
+ input [15:0] usb_data,
+ input WR,
+ input reset,
+ output reg cmd_done,
+ output reg chan_0_done,
+ output reg chan_1_done,
+ output reg WR_cmd,
+ output reg WR_chan_0,
+ output reg WR_chan_1,
+ output reg [15:0] tx_data_bus) ;
+
+ // States
+ `define IDLE 3'd0
+ `define WAIT 3'd1
+ `define READ_TARGET 3'd2
+ `define READ_LENGTH 3'd3
+ `define FORWARD_DATA 3'd4
+ `define SKIP_REST 3'd5
+
+ `define TXCHAN0 5'h0
+ `define TXCHAN1 5'h1
+ `define TXCMD 5'h1F
+
+ reg [2:0] reader_state;
+ reg [2:0] reader_next_state;
+ reg [4:0] channel;
+ reg [8:0] pkt_length;
+ reg [8:0] read_length;
+
+ // Fifo's flags
+ wire [15:0] fifodata ;
+ reg rdreq;
+ reg skip;
+ wire pkt_waiting;
+
+ // FIFO
+ usb_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(usb_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(usb_data),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .skip_packet(skip)
+ );
+
+ // FSM
+ always @(posedge tx_clock)
+ begin
+ if (reset) begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ WR_chan_0 <= 0;
+ WR_chan_1 <= 0;
+ WR_cmd <= 0;
+ end
+ else begin
+ reader_state = reader_next_state;
+ case(reader_state)
+ `IDLE: begin
+ reader_next_state <= pkt_waiting ? `WAIT : `IDLE;
+ rdreq <= pkt_waiting;
+ cmd_done <= 0;
+ chan_1_done <= 0;
+ chan_0_done <= 0;
+ end
+
+ // Wait for the fifo's data
+ `WAIT: begin
+ reader_next_state <= `READ_TARGET;
+ end
+
+ `READ_TARGET: begin
+ reader_next_state <= `READ_LENGTH;
+ cmd_done <= 0;
+ chan_1_done <= 0;
+ chan_0_done <= 0;
+
+ channel = (fifodata & 16'h1F);
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ case (channel)
+ `TXCHAN0: WR_chan_0 <= 1;
+ `TXCHAN1: WR_chan_1 <= 1;
+ `TXCMD: WR_cmd <= 1;
+ //invalid channel -> channel 0;
+ default: WR_chan_0 <= 1;
+ endcase
+ end
+
+ `READ_LENGTH: begin
+ reader_next_state <= `FORWARD_DATA;
+
+ // Plus two bytes for timestamp
+ pkt_length <= (fifodata & 16'h1FF) + 2;
+ read_length <= 9'd0;
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ end
+
+ `FORWARD_DATA: begin
+ read_length <= read_length + 2;
+
+ // If end of payload...
+ if (read_length == pkt_length) begin
+ reader_next_state <= `SKIP_REST;
+ // If the packet is 512 bytes, don't skip
+ skip <= pkt_length < 506;
+ end
+ else if (read_length == pkt_length - 2)
+ rdreq <= 0;
+
+ // Forward data
+ tx_data_bus <= fifodata;
+ end
+
+ `SKIP_REST: begin
+ reader_next_state <= pkt_waiting ? `READ_TARGET : `IDLE;
+ WR_chan_0 <= 0;
+ WR_chan_1 <= 0;
+ WR_cmd <= 0;
+ case (channel)
+ `TXCHAN0: chan_0_done <= 1;
+ `TXCHAN1: chan_0_done <= 1;
+ `TXCMD: cmd_done <= 1;
+ //invalid channel -> channel 0;
+ default: WR_chan_0 <= 1;
+ endcase
+ rdreq <= pkt_waiting;
+ skip <= 0;
+ end
+ // reset
+ default: begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+endmodule
+
+
+
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,90 @@
+module usb_packet_fifo
+ ( input reset,
+ input clock_in,
+ input clock_out,
+ input [15:0]ram_data_in,
+ input write_enable,
+ output reg [15:0]ram_data_out,
+ output reg pkt_waiting,
+ input read_enable,
+ input skip_packet ) ;
+
+ /* Some parameters for usage later on */
+ parameter DATA_WIDTH = 16 ;
+ parameter NUM_PACKETS = 4 ;
+
+ /* Create the RAM here */
+ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+ /* Create the address signals */
+ reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
+ reg [7:0] usb_ram_offset ;
+ reg [1:0] usb_ram_packet ;
+
+ wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+
+ assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
+
+ // Check if there is one full packet to process
+ always @(usb_ram_ain, usb_ram_aout)
+ begin
+ if (reset)
+ pkt_waiting <= 0;
+ else if (usb_ram_ain >= usb_ram_aout)
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ else
+ pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ end
+
+ /* RAM Write Address process */
+ always @(posedge clock_in)
+ begin
+ if( reset )
+ usb_ram_ain <= 0 ;
+ else
+ if( write_enable )
+ begin
+ usb_ram_ain <= usb_ram_ain + 1 ;
+ end
+ end
+
+ /* RAM Writing process */
+ always @(posedge clock_in)
+ begin
+ if( write_enable )
+ begin
+ usb_ram[usb_ram_ain] <= ram_data_in ;
+ end
+ end
+
+ /* RAM Read Address process */
+ always @(posedge clock_out)
+ begin
+ if( reset )
+ begin
+ usb_ram_packet <= 0 ;
+ usb_ram_offset <= 0 ;
+ end
+ else
+ if( skip_packet )
+ begin
+ usb_ram_packet <= usb_ram_packet + 1 ;
+ usb_ram_offset <= 0 ;
+ end
+ else if(read_enable)
+ if( usb_ram_offset == 8'b11111111 )
+ begin
+ usb_ram_offset <= 0 ;
+ usb_ram_packet <= usb_ram_packet + 1 ;
+ end
+ else
+ usb_ram_offset <= usb_ram_offset + 1 ;
+ end
+
+ /* RAM Reading Process */
+ always @(posedge clock_out)
+ begin
+ ram_data_out <= usb_ram[usb_ram_aout] ;
+ end
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-04-19 19:50:06 UTC (rev 5050)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-04-20 19:39:09 UTC (rev 5051)
@@ -27,7 +27,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
# Pin & Location Assignments
# ==========================
@@ -371,6 +371,12 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/usb_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/chan_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/data_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/usb_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
@@ -405,5 +411,4 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
-set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file
Added:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,122 @@
+module chan_fifo_readers_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [15:0] data_bus;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg pkt_complete;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire overrun;
+wire underrun;
+
+chan_fifo_reader chan0 (
+ .reset(reset),
+ .tx_clock(txclock),
+ .adc_clock(ttime),
+ .data_bus(data_bus),
+ .WR(WR),
+ //.debug(debug),
+ .tx_q(tx_q),
+ .tx_i(tx_i),
+ .ptk_complete(pkt_complete),
+ .overrun(overrun),
+ .underrun(underrun));
+
+
+reg [15:0] i ;
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ adcclock = 0;
+ txclock = 0;
+ data_bus = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ pkt_complete = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (20) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+ // Payload len
+ if (i == 1)
+ data_bus = 32;
+ // First 16 bits of timestamp
+ else if (i == 2)
+ data_bus = 0;
+ // 16 lower bits of timestamp
+ else if (i == 3)
+ data_bus = 1000;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ // Notify the fifo to increment the packet number
+ if (i == 19)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 1)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 2)
+ data_bus = 0;
+ // 16 lower bits of timestamp
+ else if (i == 3)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ // Notify the fifo to increment the packet number
+ if (i == 11)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+ debug = 1;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+ end
+
+always@(posedge adcclock) begin
+ ttime <= ttime + 1;
+end
+
+always
+ #5 txclock = ~txclock ;
+
+always
+ #1 adcclock = ~adcclock ;
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-20
19:39:09 UTC (rev 5051)
@@ -0,0 +1,296 @@
+[Library]
+
+; Altera specific primitive library mappings
+
+vital2000 = $MODEL_TECH/../vital2000
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+std = $MODEL_TECH/../std
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+apex20k = $MODEL_TECH/../altera/vhdl/apex20k
+apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
+apexii = $MODEL_TECH/../altera/vhdl/apexii
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
+flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
+flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
+max = $MODEL_TECH/../altera/vhdl/max
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+stratix = $MODEL_TECH/../altera/vhdl/stratix
+stratixii = $MODEL_TECH/../altera/vhdl/stratixii
+cyclone = $MODEL_TECH/../altera/vhdl/cyclone
+cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
+apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
+apexii_ver = $MODEL_TECH/../altera/verilog/apexii
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
+flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
+flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
+max_ver = $MODEL_TECH/../altera/verilog/max
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+stratix_ver = $MODEL_TECH/../altera/verilog/stratix
+stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
+cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
+cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
+stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Normally is off.
+; VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; .ini file has Explict enable so that std_logic_signed/unsigned
+; will match synthesis tools behavior.
+ Explicit = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+
+; RequireConfigForAllDefaultBinding = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turns on incremental compilation of modules
+; Incremental = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 100 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; License = plus
+
+; Stop the simulator after an assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+;CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated
+; else open files on first read or write
+; DelayFileOpen = 0
+
+; Control VHDL files opened for write
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+; This number should always be less then the
+; current ulimit setting for max file descriptors
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; This controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window. The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit
+; packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Don't quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+[Project]
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 9
+Project_File_0 = ./usb_packet_fifo_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = ./tx_buffer_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096513 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ../inband/usrp/fpga/sdr_lib/usb_fifo_reader.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177095630 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = ../inband/usrp/fpga/sdr_lib/chan_fifo_reader.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096700 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = ../inband/usrp/fpga/sdr_lib/data_packet_fifo.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/sdr_lib/usb_packet_fifo.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487356 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ./chan_fifo_readers_test.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177095370 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ./usb_fifo_reader_test.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177093134 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177096284 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 1
+ReOpenSourceFiles = 1
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+EditorState = {tabbed horizontal 1}
{Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
{Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/inband/usrp/fpga/sdr_lib/chan_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/usb_fifo_reader.v 0 0}
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0}
+Project_Major_Version = 6
+Project_Minor_Version = 1
Property changes on: gnuradio/branches/developers/thottelt/simulations/tx.mpf
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,38 @@
+module tx_buffer_test();
+
+reg usbclk;
+reg bus_reset;
+reg reset;
+reg [15:0] usbdata;
+reg WR;
+reg [3:0] channels; // ={tx_num_chan, 1b'}
+reg txclk;
+reg txstrobe;
+reg clear_status;
+
+wire have_space;
+wire tx_underrun;
+wire [15:0] tx_i_0;
+wire [15:0] tx_q_0;
+wire [15:0] tx_i_1;
+wire [15:0] tx_q_1;
+wire [15:0] tx_i_2;
+wire [15:0] tx_q_2;
+wire [15:0] tx_i_3;
+wire [15:0] tx_q_3;
+wire tx_empty;
+wire [11:0] debugbus;
+
+tx_buffer tx_buffer_test (
+ .usbclk(usbclk),
+ .reset(reset),
+ .usbdata(usbdata),
+ .WR(WR),
+ .txclk(txclk),
+ .tx_i_0(tx_i_0),
+ .tx_i_1(tx_i_1),
+ .tx_q_0(tx_q_0),
+ .tx_q_1(tx_q_1)
+);
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,106 @@
+module usb_fifo_reader_test () ;
+
+//INPUTS
+reg usb_clock;
+reg tx_clock;
+reg [15:0] usb_data;
+reg WR;
+reg reset;
+
+//OUPUTS
+wire [15:0] tx_data_bus;
+wire WR_chan_0;
+wire WR_chan_1;
+wire WR_cmd;
+
+reg [15:0] i ;
+
+usb_fifo_reader reader (
+ .reset(reset),
+ .usb_clock(usb_clock),
+ .WR(WR),
+ .tx_clock(tx_clock),
+ .tx_data_bus(tx_data_bus),
+ .WR_chan_0(WR_chan_0),
+ .WR_chan_1(WR_chan_1),
+ .WR_cmd(WR_cmd),
+ .usb_data(usb_data)
+ );
+
+
+// Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ usb_clock = 0;
+ usb_data = 0;
+ WR = 0;
+ tx_clock = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge usb_clock)
+ reset = 1'b0 ;
+ end
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usb_data = 32;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+
+ i = 0;
+
+ // Write one full packet (channel 1)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usb_data = 1;
+ else if (i == 1)
+ // payload size
+ usb_data = 504;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+
+ i = 0;
+
+ // Write one half full packet (cmd)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usb_data = 16'h1F;
+ else if (i == 1)
+ // payload size
+ usb_data = 128;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+
+ @(posedge usb_clock)
+ WR = 1'b0 ;
+ end
+
+always
+ #5 tx_clock = ~tx_clock ;
+
+always
+ #13 usb_clock = ~usb_clock ;
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
2007-04-20 19:39:09 UTC (rev 5051)
@@ -0,0 +1,89 @@
+module usb_packet_fifo_test() ;
+
+ // Inputs
+ reg reset;
+ reg clock_in;
+ reg [15:0] ram_data_in;
+ reg write_enable;
+ reg clock_out;
+ reg read_enable;
+ reg skip_packet;
+
+ reg [15:0] i ;
+
+
+ // Outputs
+ wire [15:0] ram_data_out;
+ wire is_packet;
+
+ // Instantiate the UUT
+ usb_packet_fifo uut (
+ .reset(reset),
+ .clock_in(clock_in),
+ .ram_data_in(ram_data_in),
+ .write_enable(write_enable),
+ .clock_out(clock_out),
+ .ram_data_out(ram_data_out),
+ .pkt_waiting(is_packet),
+ .read_enable(read_enable),
+ .skip_packet(skip_packet)
+ );
+
+
+ // Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ clock_in = 0;
+ ram_data_in = 0;
+ write_enable = 0;
+ clock_out = 0;
+ read_enable = 0;
+ skip_packet = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge clock_in)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (512) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ @(posedge clock_in)
+ write_enable = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+ end
+
+ always
+ #5 clock_in = ~clock_in ;
+
+ always
+ #13 clock_out = ~clock_out ;
+
+
+endmodule
+
Property changes on:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo_test.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf 2007-04-19
19:50:06 UTC (rev 5050)
+++ gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf 2007-04-20
19:39:09 UTC (rev 5051)
@@ -243,15 +243,11 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 4
-Project_File_0 = ./data_packet_fifo.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176407747 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ./chan_fifo_readers_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176418514 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_2 = ./chan_fifo_readers.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176418582 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = ../tx_usb/usb_packet_fifo.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175460531 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Files_Count = 2
+Project_File_0 = ./chan_fifo_readers_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176418514 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ../tx_usb/usb_packet_fifo.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175460531 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
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- [Commit-gnuradio] r5051 - in gnuradio/branches/developers/thottelt: . inband/usrp/fpga/sdr_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations tx_data,
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