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[Commit-gnuradio] r5064 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5064 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
|
Date: |
Sat, 21 Apr 2007 14:35:42 -0600 (MDT) |
Author: thottelt
Date: 2007-04-21 14:35:42 -0600 (Sat, 21 Apr 2007)
New Revision: 5064
Added:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
Removed:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
Log:
timestamp NOW and underrun flag added
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-04-21 19:26:54 UTC (rev 5063)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-04-21 20:35:42 UTC (rev 5064)
@@ -57,116 +57,131 @@
always @(posedge tx_clock)
begin
if (reset)
- begin
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- rdreq <= 0;
- skip <= 0;
- overrun <= 0;
- underrun <= 0;
- burst <= 0;
- end
+ begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ overrun <= 0;
+ underrun <= 0;
+ burst <= 0;
+ end
else
begin
reader_state = reader_next_state;
case (reader_state)
- `IDLE:
- begin
- reader_next_state <= pkt_waiting ? `READ : `IDLE;
- rdreq <= pkt_waiting;
- end
+ `IDLE:
+ begin
+ if (pkt_waiting == 1)
+ begin
+ reader_next_state <= `READ;
+ rdreq <= 1;
+ underrun <= 0;
+ end
+ else if (burst == 1)
+ underrun <= 1;
+ end
// Just wait for the fifo data to arrive
`READ:
- begin
- reader_next_state <= `HEADER1;
- end
+ begin
+ reader_next_state <= `HEADER1;
+ end
- // First part of the header nothing usefull
- `HEADER1:
- begin
- reader_next_state <= `HEADER2;
- end
+ // First part of the header
+ `HEADER1:
+ begin
+ reader_next_state <= `HEADER2;
+
+ //Check Start burst flag
+ if (fifodata[3] == 1)
+ burst <= 1;
+
+ if (fifodata[4] == 1)
+ burst <= 0;
+ end
// Read payload length
`HEADER2:
- begin
- payload_len <= (fifodata & 16'h1FF);
- read_len <= 9'd0;
- reader_next_state <= `TIMESTAMP1;
- end
+ begin
+ payload_len <= (fifodata & 16'h1FF);
+ read_len <= 9'd0;
+ reader_next_state <= `TIMESTAMP1;
+ end
`TIMESTAMP1:
- begin
- timestamp <= {fifodata, 16'b0};
- rdreq <= 0;
- reader_next_state <= `TIMESTAMP2;
- end
+ begin
+ timestamp <= {fifodata, 16'b0};
+ rdreq <= 0;
+ reader_next_state <= `TIMESTAMP2;
+ end
- `TIMESTAMP2:
- begin
- timestamp <= timestamp + fifodata;
- reader_next_state <= `WAIT;
- end
+ `TIMESTAMP2:
+ begin
+ timestamp <= timestamp + fifodata;
+ reader_next_state <= `WAIT;
+ end
// Decide if we wait, send or discard samples
`WAIT:
- begin
+ begin
// Wait a little bit more
- if (timestamp > adc_clock + 5)
- reader_next_state <= `WAIT;
+ if (timestamp > adc_clock + 5)
+ reader_next_state <= `WAIT;
// Prepare to send
- else if (timestamp < adc_clock + 5
- && timestamp > adc_clock)
- begin
- reader_next_state <= `SENDWAIT;
- rdreq <= 1;
- end
+ else if ((timestamp < adc_clock + 5
+ && timestamp > adc_clock)
+ || timestamp == 32'hFFFFFFFF)
+ begin
+ reader_next_state <= `SENDWAIT;
+ rdreq <= 1;
+ end
// Outdated
- else if (timestamp < adc_clock)
- begin
- reader_next_state <= `DISCARD;
- skip <= 1;
+ else if (timestamp < adc_clock)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= 1;
end
end
`SENDWAIT:
- begin
- reader_next_state <= `SEND;
- end
+ begin
+ reader_next_state <= `SEND;
+ end
// Send the samples to the tx_chain
- `SEND:
- begin
- read_len <= read_len + 2;
+ `SEND:
+ begin
+ read_len <= read_len + 2;
- // If end of payload...
- if (read_len == payload_len)
- begin
- reader_next_state <= `DISCARD;
- skip <= (payload_len < 508);
- end
- else
- begin
- if (read_len == payload_len - 4)
- rdreq <= 0;
- // Forward data
- tx_q <= fifodata;
- end
- end
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < 508);
+ end
+ else
+ begin
+ if (read_len == payload_len - 4)
+ rdreq <= 0;
+
+ // Forward data
+ tx_q <= fifodata;
+ end
+ end
- `DISCARD:
- begin
- skip <= 0;
- reader_next_state <= `IDLE;
- end
+ `DISCARD:
+ begin
+ skip <= 0;
+ reader_next_state <= `IDLE;
+ end
- default:
- begin
- $display ("Error unknown state");
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- end
+ default:
+ begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
endcase
end
end
Deleted:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v
Copied:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
(from rev 5062,
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer.v)
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
(rev 0)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-04-21 20:35:42 UTC (rev 5064)
@@ -0,0 +1,111 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+// Interface to Cypress FX2 bus
+// A packet is 512 Bytes. Each fifo line is 2 bytes
+// Fifo has 1024 or 2048 lines
+
+module tx_buffer_inband
+ ( input usbclk,
+ input bus_reset, // Used here for the 257-Hack to fix the FX2 bug
+ input reset, // standard DSP-side reset
+ input [15:0] usbdata,
+ input wire WR,
+ output wire have_space,
+ output reg tx_underrun,
+ input wire [3:0] channels,
+ output [15:0] tx_i_0,
+ output [15:0] tx_q_0,
+ output [15:0] tx_i_1,
+ output [15:0] tx_q_1,
+ //NOT USED
+ output reg [15:0] tx_i_2,
+ output reg [15:0] tx_q_2,
+ output reg [15:0] tx_i_3,
+ output reg [15:0] tx_q_3,
+ input txclk,
+ input txstrobe,
+ input clear_status,
+ output wire tx_empty,
+ output [11:0] debugbus
+ );
+
+ wire [15:0] tx_data_bus;
+ //TODO: increment it
+ reg [31:0] time_counter;
+
+ wire WR_chan_0;
+ wire chan_0_done;
+ wire OR0;
+ wire UR0;
+
+ wire WR_chan_1;
+ wire chan_1_done;
+ wire OR1;
+ wire UR1;
+
+ // NOT USED yet
+ wire WR_cmd;
+ wire cmd_done;
+
+ usb_fifo_reader usb_reader (
+ .reset(reset),
+ .usb_clock(usbclk),
+ .WR(WR),
+ .tx_clock(txclk),
+ .tx_data_bus(tx_data_bus),
+ .WR_chan_0(WR_chan_0),
+ .WR_chan_1(WR_chan_1),
+ .WR_cmd(WR_cmd),
+ .chan_0_done(chan_0_done),
+ .chan_1_done(chan_1_done),
+ .cmd_done(cmd_done),
+ .usb_data(usbdata)
+ );
+
+ chan_fifo_reader chan_0_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_0),
+ .pkt_complete(chan_0_done),
+ .tx_q(tx_q_0),
+ .tx_i(tx_i_0),
+ .overrun(OR0),
+ .underrun(UR0)
+ );
+
+ chan_fifo_reader chan_1_reader (
+ .reset(reset),
+ .tx_clock(txclk),
+ .adc_clock(time_counter),
+ .data_bus(tx_data_bus),
+ .WR(WR_chan_1),
+ .pkt_complete(chan_1_done),
+ .tx_q(tx_q_1),
+ .tx_i(tx_i_1),
+ .overrun(OR1),
+ .underrun(UR1)
+ );
+
+endmodule // tx_buffer
+
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-04-21 19:26:54 UTC (rev 5063)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-04-21 20:35:42 UTC (rev 5064)
@@ -372,10 +372,11 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/usb_packet_fifo.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/chan_fifo_reader.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/data_packet_fifo.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/usb_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/data_packet_fifo.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_reader.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-21
19:26:54 UTC (rev 5063)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-21
20:35:42 UTC (rev 5064)
@@ -244,20 +244,20 @@
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 9
-Project_File_0 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174960 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_0 = ./usb_packet_fifo_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174930 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = ./usb_packet_fifo_test.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_5 = ./tx_buffer_test.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174598 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/tx_buffer.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174685 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177187219 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177187348 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_4 = ./tx_buffer_test.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177185714 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = ./chan_fifo_readers_test.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174246 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = ./usb_fifo_reader_test.v
@@ -291,6 +291,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-21 19:26:54 UTC (rev 5063)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-21 20:35:42 UTC (rev 5064)
@@ -75,6 +75,9 @@
if (i == 1)
// payload size
usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = 16'hFFFF;
else
usbdata = i ;
i = i + 1 ;
@@ -92,6 +95,9 @@
else if (i == 1)
// payload size
usbdata = 504;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = 16'hFFFF;
else
usbdata = i ;
i = i + 1 ;
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- [Commit-gnuradio] r5064 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations,
thottelt <=