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[Commit-gnuradio] r5072 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5072 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
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Date: |
Sun, 22 Apr 2007 14:44:08 -0600 (MDT) |
Author: thottelt
Date: 2007-04-22 14:44:08 -0600 (Sun, 22 Apr 2007)
New Revision: 5072
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
Log:
refactor tx_buffer_inband + samples format handling
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-04-22 19:18:53 UTC (rev 5071)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -1,15 +1,25 @@
module chan_fifo_reader
( input reset,
input tx_clock,
+ input tx_strobe,
input [31:0]adc_clock,
- input [15:0]data_bus,
- input WR,
- input pkt_complete,
+ input [3:0] samples_format,
+ input [15:0] fifodata,
+ input pkt_waiting,
+ output reg rdreq,
+ output reg skip,
output reg [15:0]tx_q,
output reg [15:0]tx_i,
output reg overrun,
output reg underrun) ;
+ // Should not be needed if adc clock rate < tx clock rate
+ `define JITTER 5
+
+ //Samples format
+ // 16 bits interleaved complex samples
+ `define QI16 4'b0
+
// States
`define IDLE 4'd0
`define READ 4'd1
@@ -18,31 +28,12 @@
`define TIMESTAMP1 4'd4
`define TIMESTAMP2 4'd5
`define WAIT 4'd6
- `define SENDWAIT 4'd7
- `define SEND 4'd8
- `define DISCARD 4'd9
+ `define WAITSTROBE 4'd7
+ `define SENDWAIT 4'd8
+ `define SEND 4'd9
+ `define FEED 4'd10
+ `define DISCARD 4'd11
- // fifo inputs
- reg skip;
- reg rdreq;
-
- // fifo ouputs
- wire [15:0] fifodata;
- wire pkt_waiting;
-
- // Channel fifo
- data_packet_fifo tx_usb_fifo
- ( .reset(reset),
- .clock(tx_clock),
- .ram_data_in(data_bus),
- .write_enable(WR),
- .ram_data_out(fifodata),
- .pkt_waiting(pkt_waiting),
- .read_enable(rdreq),
- .pkt_complete(pkt_complete),
- .skip_packet(skip)
- );
-
// State registers
reg[3:0] reader_state;
reg[3:0] reader_next_state;
@@ -52,7 +43,7 @@
reg[8:0] read_len;
reg[31:0] timestamp;
reg burst;
-
+ reg qsample;
always @(posedge tx_clock)
begin
if (reset)
@@ -64,6 +55,7 @@
overrun <= 0;
underrun <= 0;
burst <= 0;
+ qsample <= 1;
end
else
begin
@@ -125,15 +117,14 @@
`WAIT:
begin
// Wait a little bit more
- if (timestamp > adc_clock + 5)
+ if (timestamp > adc_clock + `JITTER)
reader_next_state <= `WAIT;
- // Prepare to send
- else if ((timestamp < adc_clock + 5
+ // Let's send it
+ else if ((timestamp < adc_clock + `JITTER
&& timestamp > adc_clock)
|| timestamp == 32'hFFFFFFFF)
begin
- reader_next_state <= `SENDWAIT;
- rdreq <= 1;
+ reader_next_state <= `WAITSTROBE;
end
// Outdated
else if (timestamp < adc_clock)
@@ -142,31 +133,49 @@
skip <= 1;
end
end
+
+ // Wait for the transmit chain to be ready
+ `WAITSTROBE:
+ begin
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < 508);
+ end
+
+ if (tx_strobe == 1)
+ reader_next_state <= `SENDWAIT;
+ end
`SENDWAIT:
begin
+ rdreq <= 1;
reader_next_state <= `SEND;
end
// Send the samples to the tx_chain
`SEND:
begin
+ reader_next_state <= `WAITSTROBE;
+ rdreq <= 0;
read_len <= read_len + 2;
-
- // If end of payload...
- if (read_len == payload_len)
- begin
- reader_next_state <= `DISCARD;
- skip <= (payload_len < 508);
- end
- else
- begin
- if (read_len == payload_len - 4)
- rdreq <= 0;
-
- // Forward data
- tx_q <= fifodata;
- end
+ case(samples_format)
+ `QI16:
+ begin
+ tx_q <= qsample ? fifodata : 16'bZ;
+ tx_i <= ~qsample ? fifodata : 16'bZ;
+ qsample <= ~ qsample;
+ end
+ default:
+ begin
+ // Assume 16 bits complex samples by default
+ $display ("Error unknown samples format");
+ tx_q <= qsample ? fifodata : 16'bZ;
+ tx_i <= ~qsample ? fifodata : 16'bZ;
+ qsample <= ~ qsample;
+ end
+ endcase
end
`DISCARD:
@@ -184,5 +193,5 @@
endcase
end
end
-
+
endmodule
\ No newline at end of file
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-04-22 19:18:53 UTC (rev 5071)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -66,10 +66,25 @@
wire WR_cmd;
wire cmd_done;
- usb_fifo_reader usb_reader (
+ wire [15:0] tupf_fifodata;
+ wire tupf_pkt_waiting;
+ wire tupf_rdreq;
+ wire tupf_skip;
+
+ usb_packet_fifo tx_usb_packet_fifo
+ ( .reset(reset),
+ .clock_in(usbclk),
+ .clock_out(txclk),
+ .ram_data_in(usbdata),
+ .write_enable(WR),
+ .ram_data_out(tupf_fifodata),
+ .pkt_waiting(tupf_pkt_waiting),
+ .read_enable(tupf_rdreq),
+ .skip_packet(tupf_skip)
+ );
+
+ usb_fifo_reader tx_usb_packet_reader (
.reset(reset),
- .usb_clock(usbclk),
- .WR(WR),
.tx_clock(txclk),
.tx_data_bus(tx_data_bus),
.WR_chan_0(WR_chan_0),
@@ -78,33 +93,76 @@
.chan_0_done(chan_0_done),
.chan_1_done(chan_1_done),
.cmd_done(cmd_done),
- .usb_data(usbdata)
+ .rdreq(tupf_rdreq),
+ .skip(tupf_skip),
+ .pkt_waiting(tupf_pkt_waiting),
+ .fifodata(tupf_fifodata)
);
- chan_fifo_reader chan_0_reader (
+ wire [15:0] tdpf_fifodata_0;
+ wire tdpf_pkt_waiting_0;
+ wire tdpf_rdreq_0;
+ wire tdpf_skip_0;
+
+ data_packet_fifo tx_data_packet_fifo_0
+ ( .reset(reset),
+ .clock(txclk),
+ .ram_data_in(tx_data_bus),
+ .write_enable(WR_chan_0),
+ .ram_data_out(tdpf_fifodata_0),
+ .pkt_waiting(tdpf_pkt_waiting_0),
+ .read_enable(tdpf_rdreq_0),
+ .pkt_complete(chan_0_done),
+ .skip_packet(tdpf_skip_0)
+ );
+
+ chan_fifo_reader tx_chan_0_reader (
.reset(reset),
.tx_clock(txclk),
+ .tx_strobe(txstrobe),
.adc_clock(time_counter),
- .data_bus(tx_data_bus),
- .WR(WR_chan_0),
- .pkt_complete(chan_0_done),
+ .samples_format(4'b0),
.tx_q(tx_q_0),
.tx_i(tx_i_0),
.overrun(OR0),
- .underrun(UR0)
+ .underrun(UR0),
+ .skip(tdpf_skip_0),
+ .rdreq(tdpf_rdreq_0),
+ .fifodata(tdpf_fifodata_0),
+ .pkt_waiting(tdpf_pkt_waiting_0)
);
- chan_fifo_reader chan_1_reader (
+ wire [15:0] tdpf_fifodata_1;
+ wire tdpf_pkt_waiting_1;
+ wire tdpf_rdreq_1;
+ wire tdpf_skip_1;
+
+ data_packet_fifo tx_data_packet_fifo_1
+ ( .reset(reset),
+ .clock(txclk),
+ .ram_data_in(tx_data_bus),
+ .write_enable(WR_chan_1),
+ .ram_data_out(tdpf_fifodata_1),
+ .pkt_waiting(tdpf_pkt_waiting_1),
+ .read_enable(tdpf_rdreq_1),
+ .pkt_complete(chan_1_done),
+ .skip_packet(tdpf_skip_1)
+ );
+
+ chan_fifo_reader tx_chan_1_reader (
.reset(reset),
.tx_clock(txclk),
+ .tx_strobe(txstrobe),
.adc_clock(time_counter),
- .data_bus(tx_data_bus),
- .WR(WR_chan_1),
- .pkt_complete(chan_1_done),
+ .samples_format(4'b0),
.tx_q(tx_q_1),
.tx_i(tx_i_1),
.overrun(OR1),
- .underrun(UR1)
+ .underrun(UR1),
+ .skip(tdpf_skip_1),
+ .rdreq(tdpf_rdreq_1),
+ .fifodata(tdpf_fifodata_1),
+ .pkt_waiting(tdpf_pkt_waiting_1)
);
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-04-22 19:18:53 UTC (rev 5071)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -1,9 +1,10 @@
module usb_fifo_reader (
- input usb_clock,
input tx_clock,
- input [15:0] usb_data,
- input WR,
+ input [15:0] fifodata,
+ input pkt_waiting,
input reset,
+ output reg rdreq,
+ output reg skip,
output reg cmd_done,
output reg chan_0_done,
output reg chan_1_done,
@@ -29,25 +30,6 @@
reg [4:0] channel;
reg [8:0] pkt_length;
reg [8:0] read_length;
-
- // Fifo's flags
- wire [15:0] fifodata ;
- reg rdreq;
- reg skip;
- wire pkt_waiting;
-
- // FIFO
- usb_packet_fifo tx_usb_fifo
- ( .reset(reset),
- .clock_in(usb_clock),
- .clock_out(tx_clock),
- .ram_data_in(usb_data),
- .write_enable(WR),
- .ram_data_out(fifodata),
- .pkt_waiting(pkt_waiting),
- .read_enable(rdreq),
- .skip_packet(skip)
- );
// FSM
always @(posedge tx_clock)
Modified:
gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-04-22 19:18:53 UTC (rev 5071)
+++ gnuradio/branches/developers/thottelt/simulations/chan_fifo_readers_test.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -14,22 +14,55 @@
wire overrun;
wire underrun;
+reg [15:0] i ;
+
+// fifo inputs
+wire skip;
+wire rdreq;
+
+// fifo ouputs
+wire [15:0] fifodata;
+wire pkt_waiting;
+wire tx_strobe;
+
chan_fifo_reader chan0 (
.reset(reset),
.tx_clock(txclock),
.adc_clock(ttime),
- .data_bus(data_bus),
- .WR(WR),
+ .skip(skip),
+ .rdreq(rdreq),
+ .pkt_waiting(pkt_waiting),
+ .fifodata(fifodata),
//.debug(debug),
.tx_q(tx_q),
.tx_i(tx_i),
- .ptk_complete(pkt_complete),
.overrun(overrun),
- .underrun(underrun));
+ .underrun(underrun),
+ .samples_format(4'd0),
+ .tx_strobe(tx_strobe) );
-reg [15:0] i ;
-
+// Channel fifo
+ data_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock(txclock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip)
+ );
+
+ strobe_gen strobe_generator(
+ .reset(reset),
+ .enable(1'b1),
+ .clock(txclock),
+ .strobe_in(1'b1),
+ .strobe(tx_strobe),
+ .rate(8'd3) );
+
initial begin
// Setup the initial conditions
reset = 1;
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-22
19:18:53 UTC (rev 5071)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-22
20:44:08 UTC (rev 5072)
@@ -243,25 +243,29 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 9
-Project_File_0 = ./usb_packet_fifo_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174930 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177189399 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_3 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177187558 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = ./tx_buffer_test.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177185714 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_Files_Count = 11
+Project_File_0 = ./strobe_gen_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = ./usb_packet_fifo_test.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176487761 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177189354 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174948 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = ./chan_fifo_readers_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177174246 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ./usb_fifo_reader_test.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177093134 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177194757 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ./tx_buffer_test.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177194907 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177274378 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = ./chan_fifo_readers_test.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = ./usb_fifo_reader_test.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -291,6 +295,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/data_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/strobe_gen_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
{Z:/wc/simulations/chan_fifo_readers_test.v 0 0}
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified: gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-22 19:18:53 UTC (rev 5071)
+++ gnuradio/branches/developers/thottelt/simulations/tx_buffer_test.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -9,6 +9,8 @@
reg [3:0] channels; // ={tx_num_chan, 1b'}
reg txclk;
reg txstrobe;
+reg txstrobe1;
+reg txstrobe2;
reg clear_status;
// Outputs
@@ -28,7 +30,7 @@
// Tests
reg [15:0] i ;
-tx_buffer tx_buffer_test (
+tx_buffer_inband tx_buffer_test (
.usbclk(usbclk),
.reset(reset),
.usbdata(usbdata),
@@ -54,6 +56,8 @@
// Setup the initial conditions
reset = 1;
usbclk = 0;
+ txstrobe1 = 0;
+ txstrobe2 = 0;
usbdata = 0;
WR = 0;
txclk = 0;
@@ -104,12 +108,23 @@
end
end
+always @(posedge txclk) begin
+ if (txstrobe2 & txstrobe1 == 1)
+ begin
+ txstrobe1 <= 0;
+ txstrobe <= 1;
+ end
+ else if (txstrobe2 == 1)
+ txstrobe1 <= 1;
+ else
+ txstrobe <= 0;
+end
always
#3 txclk = ~txclk ;
always
- #3 txstrobe = ~txstrobe ;
+ #12 txstrobe2 = ~txstrobe2 ;
always
#5 usbclk = ~usbclk ;
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-04-22 19:18:53 UTC (rev 5071)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-04-22 20:44:08 UTC (rev 5072)
@@ -15,16 +15,35 @@
reg [15:0] i ;
+wire [15:0] fifodata;
+wire rdreq;
+wire skip;
+wire pkt_waiting;
+
+// FIFO
+ usb_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(usb_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(usb_data),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .skip_packet(skip)
+ );
+
usb_fifo_reader reader (
- .reset(reset),
- .usb_clock(usb_clock),
- .WR(WR),
+ .reset(reset),
.tx_clock(tx_clock),
.tx_data_bus(tx_data_bus),
.WR_chan_0(WR_chan_0),
.WR_chan_1(WR_chan_1),
.WR_cmd(WR_cmd),
- .usb_data(usb_data)
+ .fifodata(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .rdreq(rdreq),
+ .skip(skip)
);
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- [Commit-gnuradio] r5072 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations,
thottelt <=