[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5083 - in gnuradio/branches/developers/matt/u2f/top:
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r5083 - in gnuradio/branches/developers/matt/u2f/top: . u2_sim_top |
|
Date: |
Mon, 23 Apr 2007 13:00:37 -0600 (MDT) |
Author: matt
Date: 2007-04-23 13:00:36 -0600 (Mon, 23 Apr 2007)
New Revision: 5083
Added:
gnuradio/branches/developers/matt/u2f/top/u2_sim_top/
gnuradio/branches/developers/matt/u2f/top/u2_sim_top/U2_SIM.sav
gnuradio/branches/developers/matt/u2f/top/u2_sim_top/cmdfile
gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
Log:
moved
Added: gnuradio/branches/developers/matt/u2f/top/u2_sim_top/U2_SIM.sav
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim_top/U2_SIM.sav
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim_top/U2_SIM.sav
2007-04-23 19:00:36 UTC (rev 5083)
@@ -0,0 +1,95 @@
+[size] 1400 971
+[pos] -1 -1
+*-18.079937 3641000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
address@hidden
+u2_sim_top.adc_oen_a
+u2_sim_top.adc_oen_b
+u2_sim_top.adc_pdn_a
+u2_sim_top.adc_pdn_b
+u2_sim_top.aux_clk
+u2_sim_top.POR
+u2_sim_top.clk_fpga
+u2_sim_top.clk_en[1:0]
+u2_sim_top.clk_sel[1:0]
+u2_sim_top.led1
+u2_sim_top.led2
+u2_sim_top.sclk
+u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.gnt[2:0]
+u2_sim_top.sda_pad_o
+u2_sim_top.sda_pad_oen_o
+u2_sim_top.sdi
+u2_sim_top.sdo
+u2_sim_top.sen_clk
+u2_sim_top.sen_dac
+u2_sim_top.ser_enable
+u2_sim_top.ser_loopen
+u2_sim_top.ser_prbsen
+u2_sim_top.ser_rx_en
+u2_sim_top.u2_basic.sysctrl.start
+u2_sim_top.u2_basic.sysctrl.POR
+u2_sim_top.u2_basic.done
+u2_sim_top.u2_basic.sysctrl.POR
+u2_sim_top.u2_basic.sysctrl.aux_clk
+u2_sim_top.u2_basic.sysctrl.clk_fpga
+u2_sim_top.u2_basic.sysctrl.done
+u2_sim_top.u2_basic.bus_writer.start
+u2_sim_top.u2_basic.bus_writer.done
address@hidden
+u2_sim_top.u2_basic.bus_writer.rom_addr[15:0]
+u2_sim_top.u2_basic.bus_writer.rom_data[47:0]
+u2_sim_top.u2_basic.bus_writer.state[3:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_ack_i
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_adr_o[15:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_clk_i
+u2_sim_top.u2_basic.bus_writer.wb_cyc_o
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_dat_o[31:0]
+u2_sim_top.u2_basic.bus_writer.wb_sel_o[3:0]
address@hidden
+u2_sim_top.u2_basic.bus_writer.wb_stb_o
+u2_sim_top.u2_basic.bus_writer.wb_we_o
+u2_sim_top.u2_basic.bus_writer.wb_rst_i
+u2_sim_top.u2_basic.wb_conbus_top.wb_conbus_arb.req[7:0]
+u2_sim_top.sda_pad_i
+u2_sim_top.u2_basic.wb_conbus_top.m0_cyc_i
+u2_sim_top.u2_basic.wb_conbus_top.s0_cyc_o
address@hidden
+u2_sim_top.u2_basic.wb_conbus_top.m0_adr_i[15:0]
+u2_sim_top.u2_basic.wb_conbus_top.m1_adr_i[15:0]
address@hidden
+u2_sim_top.u2_basic.wb_conbus_top.m0_stb_i
+u2_sim_top.u2_basic.wb_conbus_top.m1_stb_i
+u2_sim_top.u2_basic.wb_conbus_top.s0_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s1_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s2_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s3_stb_o
+u2_sim_top.u2_basic.wb_conbus_top.s0_ack_i
+u2_sim_top.u2_basic.control_lines.wb_cyc_i
+u2_sim_top.u2_basic.control_lines.wb_stb_i
+u2_sim_top.u2_basic.control_lines.wb_we_i
+u2_sim_top.u2_basic.control_lines.wb_ack_o
+u2_sim_top.u2_basic.s0_ack
address@hidden
+u2_sim_top.u2_basic.control_lines.internal_reg[31:0]
+u2_sim_top.u2_basic.control_lines.port_output[31:0]
address@hidden
+u2_sim_top.u2_basic.led1
+u2_sim_top.u2_basic.led2
address@hidden
+u2_sim_top.u2_basic.misc_outs[7:0]
+u2_sim_top.u2_basic.clock_outs[7:0]
+u2_sim_top.u2_basic.adc_outs[7:0]
+u2_sim_top.u2_basic.serdes_outs[7:0]
address@hidden
+u2_sim_top.u2_basic.shared_spi.miso_pad_i
+u2_sim_top.u2_basic.shared_spi.mosi_pad_o
address@hidden
+u2_sim_top.u2_basic.shared_spi.ss[7:0]
+u2_sim_top.u2_basic.shared_spi.divider[15:0]
address@hidden
+u2_sim_top.u2_basic.shared_spi.sclk_pad_o
address@hidden
+u2_sim_top.u2_basic.shared_spi.ss_pad_o[7:0]
Added: gnuradio/branches/developers/matt/u2f/top/u2_sim_top/cmdfile
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim_top/cmdfile
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim_top/cmdfile
2007-04-23 19:00:36 UTC (rev 5083)
@@ -0,0 +1,8 @@
+-y ../../control_lib
+-y ../../sdr_lib
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/wb_conbus/rtl/verilog
++incdir+../../opencores/wb_conbus/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
Added: gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_sim_top/u2_sim_top.v
2007-04-23 19:00:36 UTC (rev 5083)
@@ -0,0 +1,286 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: safe_bringup
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module u2_sim_top();
+
+ // Misc, debug
+ wire led1;
+ wire led2;
+ wire [31:0] debug;
+ wire [1:0] debug_clk;
+
+ // Expansion
+ wire exp_pps_in;
+ wire exp_pps_out;
+
+ // GMII
+ // GMII-CTRL
+ wire GMII_COL;
+ wire GMII_CRS;
+
+ // GMII-TX
+ wire [7:0] GMII_TXD;
+ wire GMII_TX_EN;
+ wire GMII_TX_ER;
+ wire GMII_GTX_CLK;
+ wire GMII_TX_CLK; // 100mbps clk
+
+ // GMII-RX
+ wire [7:0] GMII_RXD;
+ wire GMII_RX_CLK;
+ wire GMII_RX_DV;
+ wire GMII_RX_ER;
+
+ // GMII-Management
+ wire MDIO;
+ wire MDC;
+ wire PHY_INTn; // open drain
+ wire PHY_RESETn;
+ wire PHY_CLK; // possibly use on-board osc
+
+ // RAM
+ wire [17:0] RAM_D;
+ wire [18:0] RAM_A;
+ wire RAM_CE1n;
+ wire RAM_CENn;
+ wire RAM_CLK;
+ wire RAM_WEn;
+ wire RAM_OEn;
+ wire RAM_LDn;
+
+ // SERDES
+ wire ser_enable;
+ wire ser_prbsen;
+ wire ser_loopen;
+
+ wire ser_tx_clk;
+ wire [15:0] ser_t;
+ wire ser_tklsb;
+ wire ser_tkmsb;
+
+ wire ser_rx_clk;
+ wire ser_rx_en;
+ wire [15:0] ser_r;
+ wire ser_rklsb;
+ wire ser_rkmsb;
+
+ // CPLD interface
+ wire spi_cpld_en;
+ wire spi_cpld_dout;
+ wire spi_cpld_din;
+ wire spi_cpld_clk; // temporary bootstrap clock
+
+ // ADC
+ wire [13:0] adc_a;
+ wire adc_ovf_a;
+ wire adc_oen_a;
+ wire adc_pdn_a;
+
+ wire [13:0] adc_b;
+ wire adc_ovf_b;
+ wire adc_oen_b;
+ wire adc_pdn_b;
+
+ // DAC
+ wire [15:0] dac_a;
+ wire [15:0] dac_b;
+
+
+ // I2C
+ wire SCL;
+ wire SDA;
+
+ // Clock Gen Control
+ wire [1:0] clk_en;
+ wire [1:0] clk_sel;
+ wire clk_func; // FIXME is an input to control the 9510
+ wire clk_status;
+
+ // Clocks
+ reg clk_fpga;
+ wire clk_to_mac;
+ wire pps_in;
+
+ // Generic SPI
+ wire sclk;
+ wire sen_clk;
+ wire sen_dac;
+ wire sdi;
+ wire sdo;
+
+ // TX DBoard
+ wire sen_tx_db;
+ wire sclk_tx_db;
+ wire sdo_tx_db;
+ wire sdi_tx_db;
+
+ wire sen_tx_adc;
+ wire sclk_tx_adc;
+ wire sdo_tx_adc;
+ wire sdi_tx_adc;
+
+ wire sen_tx_dac;
+ wire sclk_tx_dac;
+ wire sdi_tx_dac;
+
+ wire [15:0] io_tx;
+
+ // RX DBoard
+ wire sen_rx_db;
+ wire sclk_rx_db;
+ wire sdo_rx_db;
+ wire sdi_rx_db;
+
+ wire sen_rx_adc;
+ wire sclk_rx_adc;
+ wire sdo_rx_adc;
+ wire sdi_rx_adc;
+
+ wire sen_rx_dac;
+ wire sclk_rx_dac;
+ wire sdi_rx_dac;
+
+ wire [15:0] io_rx;
+
+ wire wb_clk, wb_rst;
+ wire start;
+
+ reg POR, aux_clk;
+
+ initial POR = 1'b1;
+ initial #103 POR = 1'b0;
+
+ initial aux_clk = 1'b0;
+ always #25 aux_clk = ~aux_clk;
+
+ initial clk_fpga = 1'bx;
+ initial #3007 clk_fpga = 1'b0;
+ always #7 clk_fpga = ~clk_fpga;
+
+ initial begin
+ $dumpfile("u2_sim_top.vcd");
+ $dumpvars(0,u2_sim_top);
+ end
+
+ initial #10000 $finish;
+
+ u2_basic u2_basic(/*AUTOINST*/
+ // Outputs
+ .led1 (led1),
+ .led2 (led2),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_out (exp_pps_out),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .sclk (sclk),
+ .sen_clk (sen_clk),
+ .sdi (sdi),
+ // Inputs
+ .exp_pps_in (exp_pps_in),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .RAM_D (RAM_D[17:0]),
+ .RAM_A (RAM_A[18:0]),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_rx_en (ser_rx_en),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .spi_cpld_en (spi_cpld_en),
+ .spi_cpld_dout (spi_cpld_dout),
+ //.spi_cpld_din (spi_cpld_din),
+ //.spi_cpld_clk (spi_cpld_clk),
+ .POR (POR), // FIXME
+ .aux_clk (aux_clk), // FIXME
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .scl_pad_i (scl_pad_i),
+ .sda_pad_i (sda_pad_i),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .clk_fpga (clk_fpga),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .sen_dac (sen_dac),
+ .sdo (sdo),
+ .sen_tx_db (sen_tx_db),
+ .sclk_tx_db (sclk_tx_db),
+ .sdo_tx_db (sdo_tx_db),
+ .sdi_tx_db (sdi_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sclk_tx_adc (sclk_tx_adc),
+ .sdo_tx_adc (sdo_tx_adc),
+ .sdi_tx_adc (sdi_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sclk_tx_dac (sclk_tx_dac),
+ .sdi_tx_dac (sdi_tx_dac),
+ .io_tx (io_tx[15:0]),
+ .sen_rx_db (sen_rx_db),
+ .sclk_rx_db (sclk_rx_db),
+ .sdo_rx_db (sdo_rx_db),
+ .sdi_rx_db (sdi_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sclk_rx_adc (sclk_rx_adc),
+ .sdo_rx_adc (sdo_rx_adc),
+ .sdi_rx_adc (sdi_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .sclk_rx_dac (sclk_rx_dac),
+ .sdi_rx_dac (sdi_rx_dac),
+ .io_rx (io_rx[15:0]));
+
+endmodule // u2_sim_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+//
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5083 - in gnuradio/branches/developers/matt/u2f/top: . u2_sim_top,
matt <=