[Commit-gnuradio] r5085 - gnuradio/branches/developers/matt/u2f/top/safe_bringup

[matt]

Author: matt
Date: 2007-04-23 13:05:25 -0600 (Mon, 23 Apr 2007)
New Revision: 5085

Modified:
   gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
   gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
Log:
now loads the ram from the CPLD


Modified: 
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v       
2007-04-23 19:02:59 UTC (rev 5084)
+++ gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v       
2007-04-23 19:05:25 UTC (rev 5085)
@@ -77,8 +77,8 @@
    
    // CPLD interface
    output cpld_start,  // AA9
-   output cpld_mode,   // U12
-       output cpld_done,   // V12
+   output cpld_mode,   // U12
+   output cpld_done,   // V12
    input cpld_din,   // AA14 Now Shared with CFG_Din
    input cpld_clk,   // AB14 temporary bootstrap clock
    
@@ -120,10 +120,10 @@
    input pps_in,
    
    // Generic SPI
-   output sclk,
-   output sen_clk,
+   input sclk,
+   input sen_clk,
    input sen_dac,
-   output sdi,
+   input sdi,
    input sdo,
    
    // TX DBoard
@@ -157,7 +157,7 @@
    input sen_rx_dac,
    input sclk_rx_dac,
    input sdi_rx_dac,
-
+   
    input [15:0] io_rx
    );
    
@@ -175,58 +175,54 @@
    // defparam exp_pps_out_pin.DRIVE = 12;   // FIXME  These seem to give 
errors...
                // defparam exp_pps_out_pin.SLEW = "SLOW";
    
-   wire        reset;
-   reg [31:0]  rst_ctr;
-   
-   wire        aux_clk = spi_cpld_clk;
-   assign      reset = rst_ctr[29];
-   
+   wire        aux_clk = RAM_CE1n;
+   wire        detached = RAM_A[14];
+
+   reg                 reset;
+   initial reset = 1'b1;
+
    always @(posedge aux_clk)
-     rst_ctr <= rst_ctr + 32'd1;
+     reset <= #1 1'b0;
    
-   
-   reg [23:0]  counter;
+   reg [23:0]  counter = 24'd0;
    always @(posedge aux_clk)
      counter <= #1 counter + 24'd1;
-   
-   assign      debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
+
    assign      led1 = counter[23];
    assign      led2 = 1'b0;
    assign      debug_clk[0] = aux_clk;
    assign      debug_clk[1] = clk_fpga;        
+
+   reg [7:0]   ram [0:4095];
+   wire [11:0]         ram_addr_w, ram_addr_r;
+   wire [7:0]  ram_data_w;
+   reg [7:0]   ram_data_r;
    
-   /*
-    clock_control clock_control 
-     (.reset(reset),
-      .aux_clk(aux_clk),    // 25MHz, for before fpga clock is active
-      .clk_fpga(clk_fpga),  // real 100 MHz FPGA clock
-      .clk_en(clk_en),      // controls source of reference clock
-      .clk_sel(clk_sel),    // controls source of reference clock
-      .clk_func(clk_func),  // SYNC or reset to 9510
-      .clk_status(clk_status),  // Monitor PLL or SYNC status
-      
-      .sen(sen_clk),        // Enable for the AD9510
-      .sclk(sclk),.sdi(sdo),.sdo(sdi)  // FIXME these need to be shared
-      );
-  
-   system_control (.aux_clk(),.clk_fpga(),.POR(),
-                  .dsp_clk(),.reset_out(),
-                  .wb_clk_o(),.wb_rst_o());
+   ram_loader ram_loader (.clk_i(aux_clk),.reset_i(reset),
+                         // CPLD Interface
+                         .cfg_clk_i(cpld_clk),
+                         .cfg_data_i(cpld_din),
+                         .start_o(cpld_start),
+                         .mode_o(cpld_mode),
+                         .done_o(cpld_done),
+                         .detached_i(detached),
+                         // Asynchronous RAM Interface
+                         .ram_addr(ram_addr_w),
+                         .ram_data(ram_data_w),
+                         .ram_we(ram_we) );
    
-   
-   i2c_master_top i2c (.wb_clk_i(),.wb_rst_i(),.arst_i(), 
-                      .wb_adr_i(),.wb_dat_i(),.wb_dat_o(),
-                      .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),
-                      .wb_ack_o(),.wb_inta_o,
-                      .scl_pad_i(),.scl_pad_o(),.scl_padoen_o(),
-                      .sda_pad_i(),.sda_pad_o(),.sda_padoen_o() );
+   always @(posedge aux_clk)
+     if(ram_we)
+       ram[ram_addr_w] <= #1 ram_data_w;
 
-   spi_top shared_spi
-     (.wb_clk_i(),.wb_rst_i(),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
-      .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),.wb_ack_o(),.wb_err_o(),.wb_int_o(),
-      .ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
-   */
+   always @(posedge aux_clk)
+     ram_data_r <= #1 ram[ram_addr_r];
+
+   assign     ram_addr_r = counter[15:4];
    
+   assign     debug = { ram_we, 
ram_data_r[6:0],ram_addr_r[11:4],ram_data_w,ram_addr_w[11:4]};
+
 endmodule // safe_bringup
 
 
+