[Commit-gnuradio] r5089 - gnuradio/branches/developers/matt/u2f/boot_cpld

[matt]

Author: matt
Date: 2007-04-23 14:10:40 -0600 (Mon, 23 Apr 2007)
New Revision: 5089

Modified:
   gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
   gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
Log:
now has everything to program a RAM on the FPGA


Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-23 
19:19:18 UTC (rev 5088)
+++ gnuradio/branches/developers/matt/u2f/boot_cpld/boot_cpld.v 2007-04-23 
20:10:40 UTC (rev 5089)
@@ -21,7 +21,7 @@
 module boot_cpld
   (CLK_25MHZ, CLK_25MHZ_EN, LED, CPLD_CLK, START, MODE, DONE, 
    SD_nCS, SD_Din, SD_CLK, SD_Dout, SD_DAT1, SD_DAT2, CFG_INIT_B, CFG_Din, 
DEBUG, POR, 
-   CFG_CCLK, CFG_DONE, CFG_PROG_B);
+   CFG_CCLK, CFG_DONE, CFG_PROG_B, detached);
    
    input CLK_25MHZ;
    output CLK_25MHZ_EN;
@@ -43,40 +43,35 @@
    output       CFG_CCLK;
    input        CFG_DONE;
    output       CFG_PROG_B;
-   
+   
        // To FPGA data interface
    output       CPLD_CLK;
    input        START;
    input        MODE;
-   input        DONE;
-
+   input        DONE;
+       output    detached; // to RAM_A14 (pin A11 on RAM)
    assign       CLK_25MHZ_EN = 1'b1;
    
    assign       LED[0] = ~CFG_DONE;
    assign       LED[1] = CFG_INIT_B;
    assign       LED[2] = ~CFG_PROG_B;
-   
-       reg which_clock;
-       always @(negedge POR or negedge CLK_25MHZ)
-               if(~POR)
-                       which_clock <= #1 1'b0;
-               else if(DONE)
-                       which_clock <= #1 1'b1;
-                       
-   assign       CPLD_CLK = which_clock ? CLK_25MHZ : CFG_CCLK;
-
+                       
    wire         en_outs;
    wire [3:0]   set_sel = 4'd0;
+       //  wire detached;  Now a pin
+
+       assign CPLD_CLK = CFG_CCLK;
+       assign DEBUG[7:0] = { detached, POR, CFG_PROG_B, CFG_INIT_B, CFG_DONE, 
CFG_CCLK, CFG_Din, CLK_25MHZ };
+       assign DEBUG[10:8] = { START, DONE, MODE };
+ 
+//   assign DEBUG = { /* MODE */ START, DONE, 
+//                             SD_CLK, SD_nCS, SD_Dout, SD_Din, 
+//                             CFG_PROG_B, CFG_INIT_B, CFG_DONE, CPLD_CLK, 
CFG_Din};
 
-
-   assign DEBUG = { /* MODE */ START, DONE, 
-                               SD_CLK, SD_nCS, SD_Dout, SD_Din, 
-                               CFG_PROG_B, CFG_INIT_B, CFG_DONE, CPLD_CLK, 
CFG_Din};
-
    spi_boot #(.width_set_sel_g(4),  // How many sets (16)
              .width_bit_cnt_g(6),  // Block length (12 is faster, 6 is minimum)
              .width_img_cnt_g(2),  // How many images per set
-             .num_bits_per_img_g(22), // 256 kb Image size, probably needs to 
be bigger than 18
+             .num_bits_per_img_g(20), // 256 kb Image size, probably needs to 
be bigger than 18
              .sd_init_g(1),           // SD-specific initialization
              .mmc_compat_clk_div_g(0),// No MMC support
              .width_mmc_clk_div_g(0), // No MMC support