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[Commit-gnuradio] r5133 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5133 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
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Date: |
Thu, 26 Apr 2007 17:07:04 -0600 (MDT) |
Author: thottelt
Date: 2007-04-26 17:07:04 -0600 (Thu, 26 Apr 2007)
New Revision: 5133
Added:
gnuradio/branches/developers/thottelt/simulations/4packets.dat
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
Log:
new fifo still not working
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-04-26 22:53:12 UTC (rev 5132)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-04-26 23:07:04 UTC (rev 5133)
@@ -53,17 +53,18 @@
wire tupf_skip;
wire tupf_have_space;
- usb_packet_fifo tx_usb_packet_fifo
- ( .reset(reset),
- .clock_in(usbclk),
- .clock_out(txclk),
- .ram_data_in(usbdata),
- .write_enable(WR),
- .ram_data_out(tupf_fifodata),
- .pkt_waiting(tupf_pkt_waiting),
- .read_enable(tupf_rdreq),
- .skip_packet(tupf_skip),
- .have_space(tupf_have_space)
+ usb_packet_fifo2 tx_usb_packet_fifo
+ ( .reset (reset),
+ .usb_clock (usbclk),
+ .fpga_clock (txclk),
+ .write_data (usbdata),
+ .write_enable (WR),
+ .read_data (tupf_fifodata),
+ .pkt_waiting (tupf_pkt_waiting),
+ .read_enable (tupf_rdreq),
+ .skip_packet (tupf_skip),
+ .have_space (tupf_have_space),
+ .tx_empty (tx_empty)
);
usb_fifo_reader tx_usb_packet_reader (
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-26 22:53:12 UTC (rev 5132)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-26 23:07:04 UTC (rev 5133)
@@ -22,19 +22,17 @@
/* Variable for generate statement */
genvar i ;
- /* Iterator for loop statement */
- integer j;
/* Local wires for FIFO connections */
- reg fifo_resets[2**LOG2_N-1:0] ;
- reg fifo_we[2**LOG2_N-1:0] ;
- reg fifo_re[2**LOG2_N-1:0] ;
- wire [15:0] fifo_wdata[2**LOG2_N-1:0] ;
- wire [15:0] fifo_rdata[2**LOG2_N-1:0] ;
- wire fifo_rempty[2**LOG2_N-1:0] ;
- wire fifo_rfull[2**LOG2_N-1:0] ;
- wire fifo_wempty[2**LOG2_N-1:0] ;
- wire fifo_wfull[2**LOG2_N-1:0] ;
+ wire [2**LOG2_N-1:0] fifo_resets ;
+ wire [2**LOG2_N-1:0] fifo_we ;
+ wire [2**LOG2_N-1:0] fifo_re ;
+ wire [WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ;
+ wire [WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ;
+ wire [2**LOG2_N-1:0] fifo_rempty ;
+ wire [2**LOG2_N-1:0] fifo_rfull ;
+ wire [2**LOG2_N-1:0] fifo_wempty ;
+ wire [2**LOG2_N-1:0] fifo_wfull ;
/* FIFO Select for read and write ports */
reg [LOG2_N-1:0] fifo_rselect ;
@@ -49,8 +47,8 @@
/* Assign the read_data to the output of the currently selected FIFO */
assign read_data = fifo_rdata[fifo_rselect] ;
- /* Nand over all fifo_rfull flags */
- //assign tx_empty = (fifo_rfull == LOG2_N'd0);
+ /* Figure out if we're all empty */
+ assign tx_empty = !(~fifo_rempty);
/* Increment fifo_rselect here */
always @(posedge fpga_clock)
@@ -62,52 +60,30 @@
/* Increment fifo_wselect here */
always @(posedge usb_clock)
begin
+ if (reset)
+ fifo_wselect <= {2**LOG2_N{1'b0}} ;
+
if (fifo_wfull[fifo_wselect])
fifo_wselect <= fifo_wselect + 1 ;
end
/* Route skip_packet to the correct fifo_resets signal based on the
fifo_rselect */
- always @(posedge fpga_clock)
+ always @(posedge fpga_clock, reset)
begin
- fifo_re[fifo_rselect] <= read_enable;
+ if (reset)
+ fifo_rselect <= {2**LOG2_N{1'b0}} ;
+
if (skip_packet)
- begin
- fifo_resets[fifo_rselect] <= 1 ;
fifo_rselect <= fifo_rselect + 1 ;
- end
- else
- fifo_resets[fifo_rselect] <= 0;
end
- /* Route write_enable to the correct fifo_we signal based on the
fifo_wselect */
- always @(posedge usb_clock)
- begin
- fifo_we[fifo_wselect] <= write_enable;
- end
-
- /* Initialization */
- always @(reset)
- begin
- if (reset)
- begin
- for (j = 0 ; j < 2**LOG2_N ; j = j + 1 )
- begin
- fifo_resets[j] <= 1 ;
- fifo_re[j] <= 0 ;
- fifo_we[j] <= 0 ;
- end
- fifo_wselect <= 0 ;
- fifo_rselect <= 0 ;
- end
- else
- for (j = 0 ; j < 2**LOG2_N ; j = j + 1 )
- fifo_resets[j] <= 0 ;
- end
-
/* Generate all the single packet FIFOs */
generate
for( i = 0 ; i < 2**LOG2_N ; i = i + 1 )
begin : generate_single_packet_fifos
+ assign fifo_we[i] = (fifo_wselect == i) ? write_enable : 1'b0 ;
+ assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ;
+ assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ;
assign fifo_wdata[i] = write_data ;
fifo_512 single_packet_fifo(.wrclk ( usb_clock ),
.rdclk ( fpga_clock ),
Added: gnuradio/branches/developers/thottelt/simulations/4packets.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/thottelt/simulations/4packets.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-04-26 22:53:12 UTC (rev 5132)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-04-26 23:07:04 UTC (rev 5133)
@@ -19,7 +19,7 @@
);
initial begin
- file = $fopen("packets.dat", "r");
+ file = $fopen("4packets.dat", "r");
start = 0;
count = 0;
usbclock = 0;
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-26
22:53:12 UTC (rev 5132)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-26
23:07:04 UTC (rev 5133)
@@ -247,19 +247,19 @@
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ./usb_packet_fifo2_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177536860 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177616757 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = ./fake_fx2_test.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = ./fake_fx2.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177517843 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177517843 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177539040 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177627888 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177369489 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177625462 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = ./chan_fifo_readers_test.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = ./usb_packet_fifo_test.v
@@ -305,6 +305,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/fake_fx2.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
{Z:/wc/simulations/strobe_gen_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 0} {Z:/wc/usb_packet_fifo2.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-26 22:53:12 UTC (rev 5132)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-26 23:07:04 UTC (rev 5133)
@@ -72,10 +72,8 @@
skip_packet = 1'b1 ;
@(posedge fpga_clock)
skip_packet = 1'b0 ;
-
end
-
always
#5 usb_clock = ~usb_clock;
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