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[Commit-gnuradio] r5141 - gnuradio/branches/developers/matt/u2f/top/u2_b
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r5141 - gnuradio/branches/developers/matt/u2f/top/u2_basic |
|
Date: |
Thu, 26 Apr 2007 23:42:56 -0600 (MDT) |
Author: matt
Date: 2007-04-26 23:42:56 -0600 (Thu, 26 Apr 2007)
New Revision: 5141
Modified:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ucf
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
top level seems to work in sim and fpga, with processor
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ucf
2007-04-27 01:24:56 UTC (rev 5140)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ucf
2007-04-27 05:42:56 UTC (rev 5141)
@@ -1,308 +1,314 @@
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "adc_a[0]" LOC = "A14" ;
-NET "adc_a[10]" LOC = "D20" ;
-NET "adc_a[11]" LOC = "D19" ;
-NET "adc_a[12]" LOC = "D21" ;
-NET "adc_a[13]" LOC = "E18" ;
-NET "adc_a[1]" LOC = "B14" ;
-NET "adc_a[2]" LOC = "C13" ;
-NET "adc_a[3]" LOC = "D13" ;
-NET "adc_a[4]" LOC = "A13" ;
-NET "adc_a[5]" LOC = "B13" ;
-NET "adc_a[6]" LOC = "E12" ;
-NET "adc_a[7]" LOC = "C22" ;
-NET "adc_a[8]" LOC = "C20" ;
-NET "adc_a[9]" LOC = "C21" ;
-NET "adc_b[0]" LOC = "A12" ;
-NET "adc_b[10]" LOC = "D18" ;
-NET "adc_b[11]" LOC = "B18" ;
-NET "adc_b[12]" LOC = "D17" ;
-NET "adc_b[13]" LOC = "E17" ;
-NET "adc_b[1]" LOC = "E16" ;
-NET "adc_b[2]" LOC = "F12" ;
-NET "adc_b[3]" LOC = "F13" ;
-NET "adc_b[4]" LOC = "F16" ;
-NET "adc_b[5]" LOC = "F17" ;
-NET "adc_b[6]" LOC = "C19" ;
-NET "adc_b[7]" LOC = "B20" ;
-NET "adc_b[8]" LOC = "B19" ;
-NET "adc_b[9]" LOC = "C18" ;
-NET "adc_oen_a" LOC = "E19" ;
-NET "adc_oen_b" LOC = "C17" ;
-NET "adc_ovf_a" LOC = "F18" ;
-NET "adc_ovf_b" LOC = "B17" ;
-NET "adc_pdn_a" LOC = "E20" ;
-NET "adc_pdn_b" LOC = "D15" ;
-NET "clk_en[0]" LOC = "C4" ;
-NET "clk_en[1]" LOC = "D1" ;
-NET "clk_fpga_n" LOC = "B11" ;
-NET "clk_fpga_p" LOC = "A11" ;
-NET "clk_func" LOC = "C12" ;
-NET "clk_sel[0]" LOC = "C3" ;
-NET "clk_sel[1]" LOC = "C2" ;
-NET "clk_status" LOC = "B12" ;
-NET "clk_to_mac" LOC = "AB12" ;
-NET "cpld_clk" LOC = "AB14" ;
-NET "cpld_din" LOC = "AA14" ;
-NET "cpld_done" LOC = "V12" ;
-NET "cpld_mode" LOC = "U12" ;
-NET "cpld_start" LOC = "AA9" ;
-NET "dac_a[0]" LOC = "A5" ;
-NET "dac_a[10]" LOC = "L2" ;
-NET "dac_a[11]" LOC = "L4" ;
-NET "dac_a[12]" LOC = "L3" ;
-NET "dac_a[13]" LOC = "L6" ;
-NET "dac_a[14]" LOC = "L5" ;
-NET "dac_a[15]" LOC = "K2" ;
-NET "dac_a[1]" LOC = "B5" ;
-NET "dac_a[2]" LOC = "C5" ;
-NET "dac_a[3]" LOC = "D5" ;
-NET "dac_a[4]" LOC = "A4" ;
-NET "dac_a[5]" LOC = "B4" ;
-NET "dac_a[6]" LOC = "F6" ;
-NET "dac_a[7]" LOC = "D10" ;
-NET "dac_a[8]" LOC = "D9" ;
-NET "dac_a[9]" LOC = "A10" ;
-NET "dac_b[0]" LOC = "D11" ;
-NET "dac_b[10]" LOC = "F9" ;
-NET "dac_b[11]" LOC = "A8" ;
-NET "dac_b[12]" LOC = "B8" ;
-NET "dac_b[13]" LOC = "D7" ;
-NET "dac_b[14]" LOC = "E7" ;
-NET "dac_b[15]" LOC = "B6" ;
-NET "dac_b[1]" LOC = "E11" ;
-NET "dac_b[2]" LOC = "F11" ;
-NET "dac_b[3]" LOC = "B10" ;
-NET "dac_b[4]" LOC = "C10" ;
-NET "dac_b[5]" LOC = "E10" ;
-NET "dac_b[6]" LOC = "F10" ;
-NET "dac_b[7]" LOC = "A9" ;
-NET "dac_b[8]" LOC = "B9" ;
-NET "dac_b[9]" LOC = "E9" ;
-NET "debug[0]" LOC = "N5" ;
-NET "debug[10]" LOC = "R4" ;
-NET "debug[11]" LOC = "T3" ;
-NET "debug[12]" LOC = "U3" ;
-NET "debug[13]" LOC = "M2" ;
-NET "debug[14]" LOC = "M3" ;
-NET "debug[15]" LOC = "M4" ;
-NET "debug[16]" LOC = "M5" ;
-NET "debug[17]" LOC = "M6" ;
-NET "debug[18]" LOC = "N1" ;
-NET "debug[19]" LOC = "N2" ;
-NET "debug[1]" LOC = "N6" ;
-NET "debug[20]" LOC = "N3" ;
-NET "debug[21]" LOC = "T1" ;
-NET "debug[22]" LOC = "T2" ;
-NET "debug[23]" LOC = "U2" ;
-NET "debug[24]" LOC = "T4" ;
-NET "debug[25]" LOC = "U4" ;
-NET "debug[26]" LOC = "T5" ;
-NET "debug[27]" LOC = "T6" ;
-NET "debug[28]" LOC = "U5" ;
-NET "debug[29]" LOC = "V5" ;
-NET "debug[2]" LOC = "P1" ;
-NET "debug[30]" LOC = "W2" ;
-NET "debug[31]" LOC = "W3" ;
-NET "debug[3]" LOC = "P2" ;
-NET "debug[4]" LOC = "P4" ;
-NET "debug[5]" LOC = "P5" ;
-NET "debug[6]" LOC = "R1" ;
-NET "debug[7]" LOC = "R2" ;
-NET "debug[8]" LOC = "P6" ;
-NET "debug[9]" LOC = "R5" ;
-NET "debug_clk[0]" LOC = "N4" ;
-NET "debug_clk[1]" LOC = "M1" ;
-NET "exp_pps_in_n" LOC = "V4" ;
-NET "exp_pps_in_p" LOC = "V3" ;
-NET "exp_pps_out_n" LOC = "V2" ;
-NET "exp_pps_out_p" LOC = "V1" ;
-NET "GMII_COL" LOC = "U16" ;
-NET "GMII_CRS" LOC = "U17" ;
-NET "GMII_GTX_CLK" LOC = "AA17" ;
-NET "GMII_RX_CLK" LOC = "W16" ;
-NET "GMII_RX_DV" LOC = "AB16" ;
-NET "GMII_RX_ER" LOC = "AA16" ;
-NET "GMII_RXD[0]" LOC = "AA15" ;
-NET "GMII_RXD[1]" LOC = "AB15" ;
-NET "GMII_RXD[2]" LOC = "U14" ;
-NET "GMII_RXD[3]" LOC = "V14" ;
-NET "GMII_RXD[4]" LOC = "U13" ;
-NET "GMII_RXD[5]" LOC = "V13" ;
-NET "GMII_RXD[6]" LOC = "Y13" ;
-NET "GMII_RXD[7]" LOC = "AA13" ;
-NET "GMII_TX_CLK" LOC = "W13" ;
-NET "GMII_TX_EN" LOC = "Y17" ;
-NET "GMII_TX_ER" LOC = "V16" ;
-NET "GMII_TXD[0]" LOC = "W14" ;
-NET "GMII_TXD[1]" LOC = "AA20" ;
-NET "GMII_TXD[2]" LOC = "AB20" ;
-NET "GMII_TXD[3]" LOC = "Y18" ;
-NET "GMII_TXD[4]" LOC = "AA18" ;
-NET "GMII_TXD[5]" LOC = "AB18" ;
-NET "GMII_TXD[6]" LOC = "V17" ;
-NET "GMII_TXD[7]" LOC = "W17" ;
-NET "io_rx[0]" LOC = "L21" ;
-NET "io_rx[10]" LOC = "F21" ;
-NET "io_rx[11]" LOC = "F20" ;
-NET "io_rx[12]" LOC = "G19" ;
-NET "io_rx[13]" LOC = "G18" ;
-NET "io_rx[14]" LOC = "G17" ;
-NET "io_rx[15]" LOC = "E22" ;
-NET "io_rx[1]" LOC = "L20" ;
-NET "io_rx[2]" LOC = "L19" ;
-NET "io_rx[3]" LOC = "L18" ;
-NET "io_rx[4]" LOC = "L17" ;
-NET "io_rx[5]" LOC = "K22" ;
-NET "io_rx[6]" LOC = "K21" ;
-NET "io_rx[7]" LOC = "K20" ;
-NET "io_rx[8]" LOC = "G22" ;
-NET "io_rx[9]" LOC = "G21" ;
-NET "io_tx[0]" LOC = "K4" ;
-NET "io_tx[10]" LOC = "E1" ;
-NET "io_tx[11]" LOC = "E3" ;
-NET "io_tx[12]" LOC = "F4" ;
-NET "io_tx[13]" LOC = "D2" ;
-NET "io_tx[14]" LOC = "D4" ;
-NET "io_tx[15]" LOC = "E4" ;
-NET "io_tx[1]" LOC = "K3" ;
-NET "io_tx[2]" LOC = "G1" ;
-NET "io_tx[3]" LOC = "G5" ;
-NET "io_tx[4]" LOC = "H5" ;
-NET "io_tx[5]" LOC = "F3" ;
-NET "io_tx[6]" LOC = "F2" ;
-NET "io_tx[7]" LOC = "F5" ;
-NET "io_tx[8]" LOC = "G6" ;
-NET "io_tx[9]" LOC = "E2" ;
-NET "led1" LOC = "V11" ;
-NET "led2" LOC = "Y12" ;
-NET "MDC" LOC = "V18" ;
-NET "MDIO" LOC = "Y16" ;
-NET "PHY_CLK" LOC = "V15" ;
-NET "PHY_INTn" LOC = "AB13" ;
-NET "PHY_RESETn" LOC = "AA19" ;
-NET "pps_in" LOC = "Y11" ;
-NET "RAM_A[0]" LOC = "N22" ;
-NET "RAM_A[10]" LOC = "P18" ;
-NET "RAM_A[11]" LOC = "R19" ;
-NET "RAM_A[12]" LOC = "P19" ;
-NET "RAM_A[13]" LOC = "R21" ;
-NET "RAM_A[14]" LOC = "R22" ;
-NET "RAM_A[15]" LOC = "T19" ;
-NET "RAM_A[16]" LOC = "T20" ;
-NET "RAM_A[17]" LOC = "U20" ;
-NET "RAM_A[18]" LOC = "W19" ;
-NET "RAM_A[1]" LOC = "N20" ;
-NET "RAM_A[2]" LOC = "T21" ;
-NET "RAM_A[3]" LOC = "M22" ;
-NET "RAM_A[4]" LOC = "N19" ;
-NET "RAM_A[5]" LOC = "N17" ;
-NET "RAM_A[6]" LOC = "N18" ;
-NET "RAM_A[7]" LOC = "P21" ;
-NET "RAM_A[8]" LOC = "P22" ;
-NET "RAM_A[9]" LOC = "P17" ;
-NET "RAM_CE1n" LOC = "N21" ;
-NET "RAM_CENn" LOC = "M18" ;
-NET "RAM_CLK" LOC = "M17" ;
-NET "RAM_D[0]" LOC = "Y21" ;
-NET "RAM_D[10]" LOC = "V22" ;
-NET "RAM_D[11]" LOC = "V21" ;
-NET "RAM_D[12]" LOC = "T17" ;
-NET "RAM_D[13]" LOC = "U18" ;
-NET "RAM_D[14]" LOC = "U21" ;
-NET "RAM_D[15]" LOC = "R18" ;
-NET "RAM_D[16]" LOC = "T18" ;
-NET "RAM_D[17]" LOC = "T22" ;
-NET "RAM_D[1]" LOC = "Y20" ;
-NET "RAM_D[2]" LOC = "Y19" ;
-NET "RAM_D[3]" LOC = "W22" ;
-NET "RAM_D[4]" LOC = "Y22" ;
-NET "RAM_D[5]" LOC = "V19" ;
-NET "RAM_D[6]" LOC = "W21" ;
-NET "RAM_D[7]" LOC = "W20" ;
-NET "RAM_D[8]" LOC = "U19" ;
-NET "RAM_D[9]" LOC = "V20" ;
-NET "RAM_LDn" LOC = "M21" ;
-NET "RAM_OEn" LOC = "M19" ;
-NET "RAM_WEn" LOC = "M20" ;
-NET "SCL" LOC = "A7" ;
-NET "SCL_force" LOC = "E8" ;
-NET "sclk" LOC = "K5" ;
-NET "sclk_rx_adc" LOC = "J17" ;
-NET "sclk_rx_dac" LOC = "J19" ;
-NET "sclk_rx_db" LOC = "F19" ;
-NET "sclk_tx_adc" LOC = "H1" ;
-NET "sclk_tx_dac" LOC = "J5" ;
-NET "sclk_tx_db" LOC = "D3" ;
-NET "SDA" LOC = "D8" ;
-NET "SDA_force" LOC = "C11" ;
-NET "sdi" LOC = "J1" ;
-NET "sdi_rx_adc" LOC = "H22" ;
-NET "sdi_rx_dac" LOC = "J21" ;
-NET "sdi_rx_db" LOC = "H19" ;
-NET "sdi_tx_adc" LOC = "J4" ;
-NET "sdi_tx_dac" LOC = "J6" ;
-NET "sdi_tx_db" LOC = "G4" ;
-NET "sdo" LOC = "J2" ;
-NET "sdo_rx_adc" LOC = "H21" ;
-NET "sdo_rx_db" LOC = "G20" ;
-NET "sdo_tx_adc" LOC = "H2" ;
-NET "sdo_tx_db" LOC = "G3" ;
-NET "sen_clk" LOC = "K6" ;
-NET "sen_dac" LOC = "L1" ;
-NET "sen_rx_adc" LOC = "H18" ;
-NET "sen_rx_dac" LOC = "J18" ;
-NET "sen_rx_db" LOC = "D22" ;
-NET "sen_tx_adc" LOC = "G2" ;
-NET "sen_tx_dac" LOC = "H4" ;
-NET "sen_tx_db" LOC = "C1" ;
-NET "ser_enable" LOC = "W11" ;
-NET "ser_loopen" LOC = "Y4" ;
-NET "ser_prbsen" LOC = "AA3" ;
-NET "ser_r[0]" LOC = "AB10" ;
-NET "ser_r[10]" LOC = "W10" ;
-NET "ser_r[11]" LOC = "Y1" ;
-NET "ser_r[12]" LOC = "Y3" ;
-NET "ser_r[13]" LOC = "Y2" ;
-NET "ser_r[14]" LOC = "W4" ;
-NET "ser_r[15]" LOC = "W1" ;
-NET "ser_r[1]" LOC = "AA10" ;
-NET "ser_r[2]" LOC = "U9" ;
-NET "ser_r[3]" LOC = "U6" ;
-NET "ser_r[4]" LOC = "AB11" ;
-NET "ser_r[5]" LOC = "Y7" ;
-NET "ser_r[6]" LOC = "W7" ;
-NET "ser_r[7]" LOC = "AB7" ;
-NET "ser_r[8]" LOC = "AA7" ;
-NET "ser_r[9]" LOC = "W9" ;
-NET "ser_rklsb" LOC = "V9" ;
-NET "ser_rkmsb" LOC = "Y10" ;
-NET "ser_rx_clk" LOC = "AA11" ;
-NET "ser_rx_en" LOC = "AB9" ;
-NET "ser_t[0]" LOC = "V7" ;
-NET "ser_t[10]" LOC = "AA6" ;
-NET "ser_t[11]" LOC = "Y6" ;
-NET "ser_t[12]" LOC = "W8" ;
-NET "ser_t[13]" LOC = "V8" ;
-NET "ser_t[14]" LOC = "AB8" ;
-NET "ser_t[15]" LOC = "AA8" ;
-NET "ser_t[1]" LOC = "V10" ;
-NET "ser_t[2]" LOC = "AB4" ;
-NET "ser_t[3]" LOC = "AA4" ;
-NET "ser_t[4]" LOC = "Y5" ;
-NET "ser_t[5]" LOC = "W5" ;
-NET "ser_t[6]" LOC = "AB5" ;
-NET "ser_t[7]" LOC = "AA5" ;
-NET "ser_t[8]" LOC = "W6" ;
-NET "ser_t[9]" LOC = "V6" ;
-NET "ser_tklsb" LOC = "U10" ;
-NET "ser_tkmsb" LOC = "U11" ;
-NET "ser_tx_clk" LOC = "U7" ;
-
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
+#PACE: Start of Constraints generated by PACE
+#PACE: Start of PACE I/O Pin Assignments
+NET "adc_a[0]" LOC = "A14" ;
+NET "adc_a[10]" LOC = "D20" ;
+NET "adc_a[11]" LOC = "D19" ;
+NET "adc_a[12]" LOC = "D21" ;
+NET "adc_a[13]" LOC = "E18" ;
+NET "adc_a[1]" LOC = "B14" ;
+NET "adc_a[2]" LOC = "C13" ;
+NET "adc_a[3]" LOC = "D13" ;
+NET "adc_a[4]" LOC = "A13" ;
+NET "adc_a[5]" LOC = "B13" ;
+NET "adc_a[6]" LOC = "E12" ;
+NET "adc_a[7]" LOC = "C22" ;
+NET "adc_a[8]" LOC = "C20" ;
+NET "adc_a[9]" LOC = "C21" ;
+NET "adc_b[0]" LOC = "A12" ;
+NET "adc_b[10]" LOC = "D18" ;
+NET "adc_b[11]" LOC = "B18" ;
+NET "adc_b[12]" LOC = "D17" ;
+NET "adc_b[13]" LOC = "E17" ;
+NET "adc_b[1]" LOC = "E16" ;
+NET "adc_b[2]" LOC = "F12" ;
+NET "adc_b[3]" LOC = "F13" ;
+NET "adc_b[4]" LOC = "F16" ;
+NET "adc_b[5]" LOC = "F17" ;
+NET "adc_b[6]" LOC = "C19" ;
+NET "adc_b[7]" LOC = "B20" ;
+NET "adc_b[8]" LOC = "B19" ;
+NET "adc_b[9]" LOC = "C18" ;
+NET "adc_oen_a" LOC = "E19";
+NET "adc_oen_b" LOC = "C17";
+NET "adc_ovf_a" LOC = "F18";
+NET "adc_ovf_b" LOC = "B17";
+NET "adc_pdn_a" LOC = "E20";
+NET "adc_pdn_b" LOC = "D15";
+NET "clk_en[0]" LOC = "C4" ;
+NET "clk_en[1]" LOC = "D1" ;
+NET "clk_fpga_n" LOC = "B11";
+NET "clk_fpga_p" LOC = "A11";
+NET "clk_func" LOC = "C12";
+NET "clk_sel[0]" LOC = "C3" ;
+NET "clk_sel[1]" LOC = "C2" ;
+NET "clk_status" LOC = "B12";
+NET "clk_to_mac" LOC = "AB12";
+NET "cpld_clk" LOC = "AB14";
+NET "cpld_din" LOC = "AA14";
+NET "cpld_done" LOC = "V12";
+NET "cpld_mode" LOC = "U12";
+NET "cpld_start" LOC = "AA9";
+NET "dac_a[0]" LOC = "A5" ;
+NET "dac_a[10]" LOC = "L2" ;
+NET "dac_a[11]" LOC = "L4" ;
+NET "dac_a[12]" LOC = "L3" ;
+NET "dac_a[13]" LOC = "L6" ;
+NET "dac_a[14]" LOC = "L5" ;
+NET "dac_a[15]" LOC = "K2" ;
+NET "dac_a[1]" LOC = "B5" ;
+NET "dac_a[2]" LOC = "C5" ;
+NET "dac_a[3]" LOC = "D5" ;
+NET "dac_a[4]" LOC = "A4" ;
+NET "dac_a[5]" LOC = "B4" ;
+NET "dac_a[6]" LOC = "F6" ;
+NET "dac_a[7]" LOC = "D10" ;
+NET "dac_a[8]" LOC = "D9" ;
+NET "dac_a[9]" LOC = "A10" ;
+NET "dac_b[0]" LOC = "D11" ;
+NET "dac_b[10]" LOC = "F9" ;
+NET "dac_b[11]" LOC = "A8" ;
+NET "dac_b[12]" LOC = "B8" ;
+NET "dac_b[13]" LOC = "D7" ;
+NET "dac_b[14]" LOC = "E7" ;
+NET "dac_b[15]" LOC = "B6" ;
+NET "dac_b[1]" LOC = "E11" ;
+NET "dac_b[2]" LOC = "F11" ;
+NET "dac_b[3]" LOC = "B10" ;
+NET "dac_b[4]" LOC = "C10" ;
+NET "dac_b[5]" LOC = "E10" ;
+NET "dac_b[6]" LOC = "F10" ;
+NET "dac_b[7]" LOC = "A9" ;
+NET "dac_b[8]" LOC = "B9" ;
+NET "dac_b[9]" LOC = "E9" ;
+NET "debug[0]" LOC = "N5" ;
+NET "debug[10]" LOC = "R4" ;
+NET "debug[11]" LOC = "T3" ;
+NET "debug[12]" LOC = "U3" ;
+NET "debug[13]" LOC = "M2" ;
+NET "debug[14]" LOC = "M3" ;
+NET "debug[15]" LOC = "M4" ;
+NET "debug[16]" LOC = "M5" ;
+NET "debug[17]" LOC = "M6" ;
+NET "debug[18]" LOC = "N1" ;
+NET "debug[19]" LOC = "N2" ;
+NET "debug[1]" LOC = "N6" ;
+NET "debug[20]" LOC = "N3" ;
+NET "debug[21]" LOC = "T1" ;
+NET "debug[22]" LOC = "T2" ;
+NET "debug[23]" LOC = "U2" ;
+NET "debug[24]" LOC = "T4" ;
+NET "debug[25]" LOC = "U4" ;
+NET "debug[26]" LOC = "T5" ;
+NET "debug[27]" LOC = "T6" ;
+NET "debug[28]" LOC = "U5" ;
+NET "debug[29]" LOC = "V5" ;
+NET "debug[2]" LOC = "P1" ;
+NET "debug[30]" LOC = "W2" ;
+NET "debug[31]" LOC = "W3" ;
+NET "debug[3]" LOC = "P2" ;
+NET "debug[4]" LOC = "P4" ;
+NET "debug[5]" LOC = "P5" ;
+NET "debug[6]" LOC = "R1" ;
+NET "debug[7]" LOC = "R2" ;
+NET "debug[8]" LOC = "P6" ;
+NET "debug[9]" LOC = "R5" ;
+NET "debug_clk[0]" LOC = "N4" ;
+NET "debug_clk[1]" LOC = "M1" ;
+NET "exp_pps_in_n" LOC = "V4";
+NET "exp_pps_in_p" LOC = "V3";
+NET "exp_pps_out_n" LOC = "V2";
+NET "exp_pps_out_p" LOC = "V1";
+NET "GMII_COL" LOC = "U16";
+NET "GMII_CRS" LOC = "U17";
+NET "GMII_GTX_CLK" LOC = "AA17";
+NET "GMII_RX_CLK" LOC = "W16";
+NET "GMII_RX_DV" LOC = "AB16";
+NET "GMII_RX_ER" LOC = "AA16";
+NET "GMII_RXD[0]" LOC = "AA15" ;
+NET "GMII_RXD[1]" LOC = "AB15" ;
+NET "GMII_RXD[2]" LOC = "U14" ;
+NET "GMII_RXD[3]" LOC = "V14" ;
+NET "GMII_RXD[4]" LOC = "U13" ;
+NET "GMII_RXD[5]" LOC = "V13" ;
+NET "GMII_RXD[6]" LOC = "Y13" ;
+NET "GMII_RXD[7]" LOC = "AA13" ;
+NET "GMII_TX_CLK" LOC = "W13";
+NET "GMII_TX_EN" LOC = "Y17";
+NET "GMII_TX_ER" LOC = "V16";
+NET "GMII_TXD[0]" LOC = "W14" ;
+NET "GMII_TXD[1]" LOC = "AA20" ;
+NET "GMII_TXD[2]" LOC = "AB20" ;
+NET "GMII_TXD[3]" LOC = "Y18" ;
+NET "GMII_TXD[4]" LOC = "AA18" ;
+NET "GMII_TXD[5]" LOC = "AB18" ;
+NET "GMII_TXD[6]" LOC = "V17" ;
+NET "GMII_TXD[7]" LOC = "W17" ;
+NET "io_rx[0]" LOC = "L21" ;
+NET "io_rx[10]" LOC = "F21" ;
+NET "io_rx[11]" LOC = "F20" ;
+NET "io_rx[12]" LOC = "G19" ;
+NET "io_rx[13]" LOC = "G18" ;
+NET "io_rx[14]" LOC = "G17" ;
+NET "io_rx[15]" LOC = "E22" ;
+NET "io_rx[1]" LOC = "L20" ;
+NET "io_rx[2]" LOC = "L19" ;
+NET "io_rx[3]" LOC = "L18" ;
+NET "io_rx[4]" LOC = "L17" ;
+NET "io_rx[5]" LOC = "K22" ;
+NET "io_rx[6]" LOC = "K21" ;
+NET "io_rx[7]" LOC = "K20" ;
+NET "io_rx[8]" LOC = "G22" ;
+NET "io_rx[9]" LOC = "G21" ;
+NET "io_tx[0]" LOC = "K4" ;
+NET "io_tx[10]" LOC = "E1" ;
+NET "io_tx[11]" LOC = "E3" ;
+NET "io_tx[12]" LOC = "F4" ;
+NET "io_tx[13]" LOC = "D2" ;
+NET "io_tx[14]" LOC = "D4" ;
+NET "io_tx[15]" LOC = "E4" ;
+NET "io_tx[1]" LOC = "K3" ;
+NET "io_tx[2]" LOC = "G1" ;
+NET "io_tx[3]" LOC = "G5" ;
+NET "io_tx[4]" LOC = "H5" ;
+NET "io_tx[5]" LOC = "F3" ;
+NET "io_tx[6]" LOC = "F2" ;
+NET "io_tx[7]" LOC = "F5" ;
+NET "io_tx[8]" LOC = "G6" ;
+NET "io_tx[9]" LOC = "E2" ;
+NET "led1" LOC = "V11";
+NET "led2" LOC = "Y12";
+NET "MDC" LOC = "V18";
+NET "MDIO" LOC = "Y16";
+NET "PHY_CLK" LOC = "V15";
+NET "PHY_INTn" LOC = "AB13";
+NET "PHY_RESETn" LOC = "AA19";
+NET "pps_in" LOC = "Y11";
+NET "RAM_A[0]" LOC = "N22" ;
+NET "RAM_A[10]" LOC = "P18" ;
+NET "RAM_A[11]" LOC = "R19" ;
+NET "RAM_A[12]" LOC = "P19" ;
+NET "RAM_A[13]" LOC = "R21" ;
+NET "RAM_A[14]" LOC = "R22" ;
+NET "RAM_A[15]" LOC = "T19" ;
+NET "RAM_A[16]" LOC = "T20" ;
+NET "RAM_A[17]" LOC = "U20" ;
+NET "RAM_A[18]" LOC = "W19" ;
+NET "RAM_A[1]" LOC = "N20" ;
+NET "RAM_A[2]" LOC = "T21" ;
+NET "RAM_A[3]" LOC = "M22" ;
+NET "RAM_A[4]" LOC = "N19" ;
+NET "RAM_A[5]" LOC = "N17" ;
+NET "RAM_A[6]" LOC = "N18" ;
+NET "RAM_A[7]" LOC = "P21" ;
+NET "RAM_A[8]" LOC = "P22" ;
+NET "RAM_A[9]" LOC = "P17" ;
+NET "RAM_CE1n" LOC = "N21";
+NET "RAM_CENn" LOC = "M18";
+NET "RAM_CLK" LOC = "M17";
+NET "RAM_D[0]" LOC = "Y21" ;
+NET "RAM_D[10]" LOC = "V22" ;
+NET "RAM_D[11]" LOC = "V21" ;
+NET "RAM_D[12]" LOC = "T17" ;
+NET "RAM_D[13]" LOC = "U18" ;
+NET "RAM_D[14]" LOC = "U21" ;
+NET "RAM_D[15]" LOC = "R18" ;
+NET "RAM_D[16]" LOC = "T18" ;
+NET "RAM_D[17]" LOC = "T22" ;
+NET "RAM_D[1]" LOC = "Y20" ;
+NET "RAM_D[2]" LOC = "Y19" ;
+NET "RAM_D[3]" LOC = "W22" ;
+NET "RAM_D[4]" LOC = "Y22" ;
+NET "RAM_D[5]" LOC = "V19" ;
+NET "RAM_D[6]" LOC = "W21" ;
+NET "RAM_D[7]" LOC = "W20" ;
+NET "RAM_D[8]" LOC = "U19" ;
+NET "RAM_D[9]" LOC = "V20" ;
+NET "RAM_LDn" LOC = "M21";
+NET "RAM_OEn" LOC = "M19";
+NET "RAM_WEn" LOC = "M20";
+NET "SCL" LOC = "A7";
+NET "SCL_force" LOC = "E8";
+NET "sclk" LOC = "K5";
+NET "sclk_rx_adc" LOC = "J17";
+NET "sclk_rx_dac" LOC = "J19";
+NET "sclk_rx_db" LOC = "F19";
+NET "sclk_tx_adc" LOC = "H1";
+NET "sclk_tx_dac" LOC = "J5";
+NET "sclk_tx_db" LOC = "D3";
+NET "SDA" LOC = "D8";
+NET "SDA_force" LOC = "C11";
+NET "sdi" LOC = "J1";
+NET "sdi_rx_adc" LOC = "H22";
+NET "sdi_rx_dac" LOC = "J21";
+NET "sdi_rx_db" LOC = "H19";
+NET "sdi_tx_adc" LOC = "J4";
+NET "sdi_tx_dac" LOC = "J6";
+NET "sdi_tx_db" LOC = "G4";
+NET "sdo" LOC = "J2";
+NET "sdo_rx_adc" LOC = "H21";
+NET "sdo_rx_db" LOC = "G20";
+NET "sdo_tx_adc" LOC = "H2";
+NET "sdo_tx_db" LOC = "G3";
+NET "sen_clk" LOC = "K6";
+NET "sen_dac" LOC = "L1";
+NET "sen_rx_adc" LOC = "H18";
+NET "sen_rx_dac" LOC = "J18";
+NET "sen_rx_db" LOC = "D22";
+NET "sen_tx_adc" LOC = "G2";
+NET "sen_tx_dac" LOC = "H4";
+NET "sen_tx_db" LOC = "C1";
+NET "ser_enable" LOC = "W11";
+NET "ser_loopen" LOC = "Y4";
+NET "ser_prbsen" LOC = "AA3";
+NET "ser_r[0]" LOC = "AB10" ;
+NET "ser_r[10]" LOC = "W10" ;
+NET "ser_r[11]" LOC = "Y1" ;
+NET "ser_r[12]" LOC = "Y3" ;
+NET "ser_r[13]" LOC = "Y2" ;
+NET "ser_r[14]" LOC = "W4" ;
+NET "ser_r[15]" LOC = "W1" ;
+NET "ser_r[1]" LOC = "AA10" ;
+NET "ser_r[2]" LOC = "U9" ;
+NET "ser_r[3]" LOC = "U6" ;
+NET "ser_r[4]" LOC = "AB11" ;
+NET "ser_r[5]" LOC = "Y7" ;
+NET "ser_r[6]" LOC = "W7" ;
+NET "ser_r[7]" LOC = "AB7" ;
+NET "ser_r[8]" LOC = "AA7" ;
+NET "ser_r[9]" LOC = "W9" ;
+NET "ser_rklsb" LOC = "V9";
+NET "ser_rkmsb" LOC = "Y10";
+NET "ser_rx_clk" LOC = "AA11";
+NET "ser_rx_en" LOC = "AB9";
+NET "ser_t[0]" LOC = "V7" ;
+NET "ser_t[10]" LOC = "AA6" ;
+NET "ser_t[11]" LOC = "Y6" ;
+NET "ser_t[12]" LOC = "W8" ;
+NET "ser_t[13]" LOC = "V8" ;
+NET "ser_t[14]" LOC = "AB8" ;
+NET "ser_t[15]" LOC = "AA8" ;
+NET "ser_t[1]" LOC = "V10" ;
+NET "ser_t[2]" LOC = "AB4" ;
+NET "ser_t[3]" LOC = "AA4" ;
+NET "ser_t[4]" LOC = "Y5" ;
+NET "ser_t[5]" LOC = "W5" ;
+NET "ser_t[6]" LOC = "AB5" ;
+NET "ser_t[7]" LOC = "AA5" ;
+NET "ser_t[8]" LOC = "W6" ;
+NET "ser_t[9]" LOC = "V6" ;
+NET "ser_tklsb" LOC = "U10";
+NET "ser_tkmsb" LOC = "U11";
+NET "ser_tx_clk" LOC = "U7";
+#PACE: Start of PACE Area Constraints
+#PACE: Start of PACE Prohibit Constraints
+#PACE: End of Constraints generated by PACE
+NET "clk_fpga_n" TNM_NET = "clk_fpga_n";
+TIMESPEC "TS_clk_fpga_n" = PERIOD "clk_fpga_n" 10 ns HIGH 50 %;
+NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
+TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns LOW 50 %;
+NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
+TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
+NET "u2_basic/sysctrl/half_clk" TNM_NET = "u2_basic/sysctrl/half_clk";
+TIMESPEC "TS_u2_basic_sysctrl_half_clk" = PERIOD "u2_basic/sysctrl/half_clk"
"TS_clk_fpga_n" * 2;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-27 01:24:56 UTC (rev 5140)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-27 05:42:56 UTC (rev 5141)
@@ -1,15 +1,29 @@
-`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
-// Module Name: safe_bringup
+// Module Name: u2_basic
//
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
//
+// Wishbone setup
+// 2 Masters
+// 0 System controller, to set up AD9510 and clocks and load RAM
+// 1 Main Processor (aeMB)
+
+// Address bus is 16 bits. Top 4 addr bits select the slave
+// 0 System RAM
+// 1 General SPI
+// 2 I2C
+// 3 GPIOs for TX and RX DB
+// 4 Output control lines
+// 5 SPI - TXDB
+// 6 SPI - TXDAC
+// 7 SPI - TXADC
+// 8 SPI - TXDB
+// 9 SPI - TXDAC
+// 10 SPI - TXADC
+// 11 Interrupt controller?
+// 12 MDC for PHY?
+//
//////////////////////////////////////////////////////////////////////////////////
-// Nearly everything is an input
-
module u2_basic
(
// Clocks
@@ -148,35 +162,22 @@
inout [15:0] io_rx
);
- wire dsp_clk, wb_clk, wb_rst, reset;
-
- assign debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
+ wire dsp_clk, wb_clk, clock_ready, ram_loader_done;
+ wire ram_loader_rst, processor_rst, wb_rst, dsp_rst;
+ wire [7:0] sysctrl_dbg;
+
+ assign
debug={{ram_loader_done,clock_ready,dsp_clk,wb_clk,ram_loader_rst,processor_rst,wb_rst,dsp_rst},
+
{1'b0,cpld_start,cpld_mode,cpld_done,1'b0,cpld_din,cpld_clk,cpld_detached},
+ {sysctrl_dbg},
+ {2'b0, clk_status, sen_dac, sen_clk, sclk, sdi, sdo}};
assign debug_clk[0] = aux_clk;
assign debug_clk[1] = clk_fpga;
- // 2 Masters
- // 0 System controller, to set up AD9510 and clocks
- // 1 Main Processor (aeMB)
-
- // Address bus is 16 bits. Top 4 addr bits select the slave
- // 0 System RAM
- // 1 General SPI
- // 2 I2C
- // 3 GPIOs for TX and RX DB
- // 4 Output control lines
- // 5 SPI - TXDB
- // 6 SPI - TXDAC
- // 7 SPI - TXADC
- // 8 SPI - TXDB
- // 9 SPI - TXDAC
- // 10 SPI - TXADC
- // 11 Interrupt controller?
-
-
parameter dw = 32; // Data bus width
parameter aw = 16; // Address bus width, for byte addressibility, 16 =
64K byte memory space
parameter sw = 4; // Select width -- 32-bit data bus with 8-bit
granularity.
// FIXME Does this mean we ignore the bottom 2 address bits? or should they
not be there?
+ // Or does the bottom bit address the double word?
// Wishbone signals
wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
@@ -192,44 +193,34 @@
wire m0_we, m1_we, s0_we, s1_we, s2_we, s3_we, s4_we, s5_we, s6_we,
s7_we;
wire m0_cab, m1_cab, s0_cab, s1_cab, s2_cab, s3_cab, s4_cab,
s5_cab, s6_cab, s7_cab;
- //
////////////////////////////////////////////////////////////////////////////////////
- // Output control lines, SLAVE #4
- // organized in 4 8-bit segments -- clock, serdes, adc, led+misc
-
- //
/////////////////////////////////////////////////////////////////////////////////////////
- // Bootstrap RAM
- reg [7:0] ram [0:4095];
- wire [11:0] ram_addr_w, ram_addr_r;
- wire [7:0] ram_data_w;
- reg [7:0] ram_data_r;
-
- ram_loader ram_loader (.clk_i(aux_clk),.reset_i(reset),
+
//////////////////////////////////////////////////////////////////////////////////////////
+ // System Controller, handles reset and clocks
+ system_control sysctrl (.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
+ .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
+
.ram_loader_rst_o(ram_loader_rst),.processor_rst_o(processor_rst),
+ .wb_rst_o(wb_rst),.dsp_rst_o(dsp_rst),
+
.ram_loader_done_i(ram_loader_done),.clock_ready_i(clock_ready),
+ .debug_o(sysctrl_dbg) );
+
+ /////////////////////////////////////////////////////////////////////
+ // Master #0 -- RAM Loader
+ ram_loader ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
// CPLD Interface
.cfg_clk_i(cpld_clk),
.cfg_data_i(cpld_din),
.start_o(cpld_start),
.mode_o(cpld_mode),
.done_o(cpld_done),
- .detached_i(detached),
- // Asynchronous RAM Interface
- .ram_addr(ram_addr_w),
- .ram_data(ram_data_w),
- .ram_we(ram_we) );
+ .detached_i(cpld_detached),
+ // Wishbone Interface
+ .wb_dat_o(m0_dat_i),.wb_adr_o(m0_adr[11:0]),
+ .wb_stb_o(m0_stb),.wb_cyc_o(m0_cyc),.wb_sel_o(m0_sel),
+ .wb_we_o(m0_we),.wb_ack_i(m0_ack),
+ .ram_loader_done_o(ram_loader_done));
- always @(posedge aux_clk)
- if(ram_we)
- ram[ram_addr_w] <= #1 ram_data_w;
-
- always @(posedge aux_clk)
- ram_data_r <= #1 ram[ram_addr_r];
+ assign m0_adr[15:12] = 4'h0; // Always talk to RAM, slave #0
+ assign m0_cab = 1'b0;
- wire [15:0] counter;
-
- assign ram_addr_r = counter[15:4];
-
- wire [15:0] rom_addr;
- wire [47:0] rom_data;
-
//
//////////////////////////////////////////////////////////////////////////////////////////
// Master # 1 -- Internal processor
@@ -237,49 +228,21 @@
wire [aw-1:0] iwb_adr;
wire [dw-1:0] iwb_dat;
- aeMB_core #(.ISIZ(16),.DSIZ(32))
- aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
+ aeMB_core_BE #(.ISIZ(16),.DSIZ(16))
+ aeMB (.sys_clk_i(wb_clk), .sys_rst_i(processor_rst),
// Instruction Wishbone bus to I-RAM
.iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
.iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
// Data Wishbone bus to system bus fabric
.dwb_we_o(m1_we),.dwb_stb_o(m1_stb),.dwb_dat_o(m1_dat_i),.dwb_adr_o(m1_adr),
- .dwb_dat_i(m1_dat_o),.dwb_ack_i(m1_ack),
+
.dwb_dat_i(m1_dat_o),.dwb_ack_i(m1_ack),.dwb_sel_o(m1_sel),.dwb_cyc_o(m1_cyc),
// Interrupts and exceptions
.sys_int_i(proc_int),.sys_exc_i(bus_error) );
- assign m1_cab = 1'b0;
- assign m1_sel = 4'b1111; // Until core can do byte-addressing
- assign m1_cyc = m1_stb; // Until core properly drives this
+ assign m1_cab = 1'b0; // Old signal on CONBUS
assign bus_error = m1_err | m1_rty;
assign proc_int = 1'b0;
-
////////////////////////////////////////////////////////////////////////////////////////
- // Clock bootstrapping
- clock_bootstrap_rom cbrom(.addr(rom_addr),.data(rom_data));
-
- wb_bus_writer bus_writer(.rom_addr (rom_addr),
- .wb_dat_o (m0_dat_i),
- .wb_adr_o (m0_adr),
- .wb_cyc_o (m0_cyc),
- .wb_sel_o (m0_sel),
- .wb_stb_o (m0_stb),
- .wb_we_o (m0_we),
- .start (start),
- .done (done),
- .rom_data (rom_data),
- .wb_clk_i (wb_clk),
- .wb_rst_i (wb_rst),
- .wb_ack_i (m0_ack));
- assign m0_cab = 1'b0;
-
-
//////////////////////////////////////////////////////////////////////////////////////////
- // Master # 0 -- System Controller, handles reset and clocks
- system_control sysctrl (.aux_clk(aux_clk),.clk_fpga(clk_fpga),.POR(POR),
- .dsp_clk(dsp_clk),.reset_out(reset),
- .wb_clk_o(wb_clk),.wb_rst_o(wb_rst),.wb_rst_o_alt(),
- .start(start),.done(done) );
-
//
/////////////////////////////////////////////////////////////////////////////////////////
// Dual Ported RAM -- Slave #0
// I-port connects directly to processor, D-port connects to bus (slave 0)
@@ -288,7 +251,7 @@
ID_ram (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
.iwb_adr_i(iwb_adr),.iwb_dat_o(iwb_dat),.iwb_stb_i(iwb_stb),.iwb_ack_o(iwb_ack),
.dwb_adr_i(s0_adr),.dwb_dat_i(s0_dat_o),.dwb_dat_o(s0_dat_i),
- .dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb));
+
.dwb_we_i(s0_we),.dwb_ack_o(s0_ack),.dwb_stb_i(s0_stb),.dwb_sel_i(s0_sel));
// SPI -- Slave #1
spi_top shared_spi
@@ -308,7 +271,9 @@
// GPIOs -- Slave #3
wire s3_ack_a, s3_ack_b, s3_ack_c, s3_ack_d;
- assign s3_ack = s3_ack_a | s3_ack_b | s3_ack_c | s3_ack_d;
+ assign s3_ack = 1'b0;
+
+/* assign s3_ack = s3_ack_a | s3_ack_b | s3_ack_c | s3_ack_d;
simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(wb_rst),
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[0]),.adr_i(s3_adr),.we_i(s3_we),
@@ -329,13 +294,15 @@
.cyc_i(s3_cyc),.stb_i(s3_stb&s3_sel[3]),.adr_i(s3_adr),.we_i(s3_we),
.dat_i(s3_dat_o[31:24]),.dat_o(s3_dat_i[31:24]),.ack_o(s3_ack_d),
.gpio(io_rx[15:8]) );
-
- // Basic Outputs -- Slave #4
+ */
+ //
////////////////////////////////////////////////////////////////////////////////////
+ // Output control lines, SLAVE #4
+ // organized in 4 8-bit segments -- clock, serdes, adc, led+misc
wire [7:0] clock_outs, serdes_outs, adc_outs, misc_outs;
- assign {clk_en[1:0], clk_sel[1:0]} = clock_outs[3:0]; //= { 4'b0,
clk_en[1:0], clk_sel[1:0] };
- assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} =
serdes_outs[3:0]; // = { 4'b0, ser_enable, ser_prbsen, ser_loopen, ser_rx_en };
- assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } =
adc_outs[3:0]; // = { 4'b0, adc_oe_a_n, adc_pdn_a, adc_oe_b_n, adc_pdn_b };
- assign {led2, led1} = misc_outs[1:0]; // = { 6'b0, led2, led1 };
+ assign {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
+ assign {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} =
serdes_outs[3:0];
+ assign { adc_oen_a, adc_pdn_a, adc_oen_b, adc_pdn_b } = adc_outs[3:0];
+ assign {led2, led1} = misc_outs[1:0];
wb_output_pins32 control_lines
(.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(s4_dat_o),.wb_dat_o(s4_dat_i),
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