[Commit-gnuradio] r5148 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-04-27 00:15:20 -0600 (Fri, 27 Apr 2007)
New Revision: 5148

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/SYSCTRL.sav
   gnuradio/branches/developers/matt/u2f/control_lib/system_control_tb.v
Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
   gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
Log:
system controller seems complete at this time


Added: gnuradio/branches/developers/matt/u2f/control_lib/SYSCTRL.sav
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/SYSCTRL.sav               
                (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/SYSCTRL.sav       
2007-04-27 06:15:20 UTC (rev 5148)
@@ -0,0 +1,24 @@
+[size] 1400 971
+[pos] -1 -1
+*-11.026821 2450 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 
-1 -1 -1 -1 -1 -1
address@hidden
+system_control_tb.aux_clk
address@hidden
+system_control_tb.clk_fpga
address@hidden
+system_control_tb.dsp_clk
+system_control_tb.dsp_rst
+system_control_tb.proc_rst
+system_control_tb.rl_done
+system_control_tb.rl_rst
+system_control_tb.wb_clk
+system_control_tb.wb_rst
+system_control_tb.system_control.POR
address@hidden
+system_control_tb.system_control.POR_ctr[3:0]
address@hidden
+system_control_tb.clock_ready
+system_control_tb.system_control.half_clk
+system_control_tb.system_control.fin_ret_half
+system_control_tb.system_control.fin_ret_aux
+system_control_tb.system_control.gate_dsp_clk

Modified: gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v      
2007-04-27 06:12:38 UTC (rev 5147)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ram_loader.v      
2007-04-27 06:15:20 UTC (rev 5148)
@@ -1,26 +1,36 @@
 
+// Adapted from VHDL code in spi_boot by Arnim Legauer
+//  Added a full wishbone master interface (32-bit)
 
-module ram_loader (input clk_i, input reset_i,
-                  input cfg_clk_i, input cfg_data_i,
-                  output start_o, output mode_o, output done_o,
-                  input detached_i,
-                  output [11:0] ram_addr,
-                  output [7:0] ram_data,
-                  output ram_we);
+module ram_loader #(parameter AWIDTH=12)
+  (input clk_i, input rst_i,
+   // CPLD Interface
+   input cfg_clk_i, input cfg_data_i,
+   output start_o, output mode_o, output done_o,
+   input detached_i,
+   // Wishbone interface
+   output wire [31:0] wb_dat_o,
+   output reg [AWIDTH-1:0] wb_adr_o,
+   output wb_stb_o,
+   output wb_cyc_o,
+   output reg [3:0] wb_sel_o,
+   output reg wb_we_o,
+   input wb_ack_i,
+   output ram_loader_done_o);
    
    //  FSM to control start signal, clocked on main clock
-`define FSM1_WAIT_DETACH  2'b00
-`define FSM1_CHECK_NO_DONE  2'b01
-`define FSM1_WAIT_DONE  2'b10
+   localparam FSM1_WAIT_DETACH = 2'b00;
+   localparam FSM1_CHECK_NO_DONE = 2'b01;
+   localparam FSM1_WAIT_DONE = 2'b10;
    
-   reg [1:0]             start_fsm_q, start_fsm_s;
-   reg                           start_q, enable_q, start_s, enable_s;
-   reg                           done_q, done_s;
+   reg [1:0]  start_fsm_q, start_fsm_s;
+   reg               start_q, enable_q, start_s, enable_s;
+   reg               done_q, done_s;
    
-   always @(posedge clk_i or posedge reset_i)
-     if(reset_i)
+   always @(posedge clk_i or posedge rst_i)
+     if(rst_i)
        begin
-         start_fsm_q <= #1 `FSM1_WAIT_DETACH;
+         start_fsm_q <= #1 FSM1_WAIT_DETACH;
          start_q <= #1 1'b0;
          enable_q <= #1 1'b0;
        end
@@ -29,82 +39,80 @@
          start_fsm_q <= #1 start_fsm_s;
          enable_q <= #1 enable_s;
          start_q <= #1 start_s;
-       end // else: !if(reset_i)
-
+       end // else: !if(rst_i)
+   
    always @*
      case(start_fsm_q)
-       `FSM1_WAIT_DETACH:
+       FSM1_WAIT_DETACH:
         if(detached_i == 1'b1)
           begin
-             start_fsm_s <= `FSM1_CHECK_NO_DONE;
+             start_fsm_s <= FSM1_CHECK_NO_DONE;
              enable_s <= 1'b1;
              start_s <= 1'b1;
           end
         else
           begin
-             start_fsm_s <= `FSM1_WAIT_DETACH;
+             start_fsm_s <= FSM1_WAIT_DETACH;
              enable_s <= enable_q;
              start_s <= start_q;
           end // else: !if(detached_i == 1'b1)
-       `FSM1_CHECK_NO_DONE:
+       FSM1_CHECK_NO_DONE:
         if(~done_q)
           begin
-             start_fsm_s  <= `FSM1_WAIT_DONE;
+             start_fsm_s  <= FSM1_WAIT_DONE;
              enable_s <= enable_q;
              start_s <= start_q;
           end
         else
           begin
-             start_fsm_s  <= `FSM1_CHECK_NO_DONE;
+             start_fsm_s  <= FSM1_CHECK_NO_DONE;
              enable_s <= enable_q;
              start_s <= start_q;
           end // else: !if(~done_q)
-       `FSM1_WAIT_DONE:
+       FSM1_WAIT_DONE:
         if(done_q)
           begin
-             start_fsm_s  <= `FSM1_WAIT_DETACH;
+             start_fsm_s  <= FSM1_WAIT_DETACH;
              enable_s <= 1'b0;
              start_s <= 1'b0;
           end
         else
           begin
-             start_fsm_s  <= `FSM1_WAIT_DONE;
+             start_fsm_s  <= FSM1_WAIT_DONE;
              enable_s <= enable_q;
              start_s <= start_q;
           end // else: !if(done_q)
        default:
         begin
-           start_fsm_s  <= `FSM1_WAIT_DETACH;
+           start_fsm_s  <= FSM1_WAIT_DETACH;
            enable_s <= enable_q;
            start_s <= start_q;
         end // else: !if(done_q)
      endcase // case(start_fsm_q)
    
-          
-          
-//  FSM running on data clock
+   //  FSM running on data clock
 
-`define FSM2_IDLE 3'b000
-`define FSM2_WE_ON 3'b001
-`define FSM2_WE_OFF 3'b010
-`define FSM2_INC_ADDR1 3'b011
-`define FSM2_INC_ADDR2 3'b100
-`define FSM2_FINISHED 3'b101
-
-   reg [11:0] addr_q;
-   reg [7:0]  shift_dat_q, ser_dat_q;
-   reg [2:0]  bit_q, fsm_q, fsm_s;
-   reg               bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, 
inc_addr_s;
+   localparam FSM2_IDLE = 3'b000;
+   localparam FSM2_WE_ON = 3'b001;
+   localparam FSM2_WE_OFF = 3'b010;
+   localparam FSM2_INC_ADDR1 = 3'b011;
+   localparam FSM2_INC_ADDR2 = 3'b100;
+   localparam FSM2_FINISHED = 3'b101;
    
-   always @(posedge cfg_clk_i or posedge reset_i)
-     if(reset_i)
+   reg [AWIDTH-1:0] addr_q;
+   reg [7:0]       shift_dat_q, ser_dat_q;
+   reg [2:0]       bit_q, fsm_q, fsm_s;
+   reg                     bit_ovfl_q, ram_we_s, ram_we_q, mode_q, mode_s, 
inc_addr_s;
+   
+   always @(posedge cfg_clk_i or posedge rst_i)
+     if(rst_i)
        begin
-         addr_q <= #1 12'd0;
+         addr_q <= #1 0;
          shift_dat_q <= #1 8'd0;
          ser_dat_q <= #1 8'd0;
          bit_q <= #1 3'd0;
          bit_ovfl_q <= #1 1'b0;
-         fsm_q <= #1 `FSM2_IDLE;
+         fsm_q <= #1 FSM2_IDLE;
          ram_we_q <= #1 1'b0;
          done_q <= #1 1'b0;
          mode_q <= #1 1'b0;
@@ -112,7 +120,7 @@
      else
        begin
          if(inc_addr_s)
-           addr_q <= #1 addr_q + 12'd1;
+           addr_q <= #1 addr_q + 1;
          if(enable_q)
            begin
               bit_q <= #1 bit_q + 1;
@@ -130,55 +138,85 @@
          if(done_s)
            done_q <= #1 1'b1;
          mode_q <= mode_s;
-       end // else: !if(reset_i)
+       end // else: !if(rst_i)
 
    always @*
      begin
        inc_addr_s <= 1'b0;
        ram_we_s <= 1'b0;
        done_s <= 1'b0;
-       fsm_s <= `FSM2_IDLE;
+       fsm_s <= FSM2_IDLE;
        mode_s <= 1'b0;
 
        case(fsm_q)
-         `FSM2_IDLE :
+         FSM2_IDLE :
            if(start_q)
              if(bit_ovfl_q)
-               fsm_s <= `FSM2_WE_ON;
-         `FSM2_WE_ON:
+               fsm_s <= FSM2_WE_ON;
+         FSM2_WE_ON:
            begin
               ram_we_s <= 1'b1;
-              fsm_s <= `FSM2_WE_OFF;
+              fsm_s <= FSM2_WE_OFF;
            end
-         `FSM2_WE_OFF:
-           fsm_s <= `FSM2_INC_ADDR1;
-         `FSM2_INC_ADDR1:
-           fsm_s <= `FSM2_INC_ADDR2;
-         `FSM2_INC_ADDR2:
-           if(addr_q == 12'h3FF)
+         FSM2_WE_OFF:
+           fsm_s <= FSM2_INC_ADDR1;
+         FSM2_INC_ADDR1:
+           fsm_s <= FSM2_INC_ADDR2;
+         FSM2_INC_ADDR2:
+           if(&addr_q)
              begin
-                fsm_s <= `FSM2_FINISHED;
+                fsm_s <= FSM2_FINISHED;
                 done_s <= 1'b1;
                 mode_s <= 1'b1;
              end
            else
              begin
                 inc_addr_s <= 1'b1;
-                fsm_s <= `FSM2_IDLE;
-             end // else: !if(addr_q == 12'h0FF)
-         `FSM2_FINISHED:
+                fsm_s <= FSM2_IDLE;
+             end // else: !if(&addr_q)
+         FSM2_FINISHED:
            begin
-              fsm_s <= `FSM2_FINISHED;
+              fsm_s <= FSM2_FINISHED;
               mode_s <= 1'b1;
            end
        endcase // case(fsm_q)
      end // always @ *
-
+   
    assign start_o = start_q;
    assign mode_o = mode_q;
    assign done_o = start_q ? done_q : 1'b1;
-   assign ram_addr = addr_q;
-   assign ram_data = ser_dat_q;
+   wire [AWIDTH-1:0] ram_addr = addr_q;
+   wire [7:0] ram_data = ser_dat_q;
    assign ram_we = ram_we_q;
+   assign ram_loader_done_o = (fsm_q == FSM2_FINISHED);
    
+   // wishbone master, only writes.  May be somewhat superfluous...
+   reg [7:0] dat_holder;
+   assign    wb_dat_o = {4{dat_holder}};
+   assign    wb_stb_o = wb_we_o;
+   assign    wb_cyc_o = wb_we_o;
+   
+   always @(posedge clk_i or posedge rst_i)
+     if(rst_i)
+       begin
+         dat_holder <= 8'd0;
+         wb_adr_o <= 0;
+         wb_sel_o <= 4'b0000;
+         wb_we_o <= 1'b0;
+       end
+     else if(ram_we)
+       begin
+         dat_holder <= ram_data;
+         wb_adr_o <= ram_addr;
+         wb_we_o <= 1'b1;
+         case(ram_addr[1:0])   // Big Endian
+           2'b00 : wb_sel_o <= 4'b1000;
+           2'b01 : wb_sel_o <= 4'b0100;
+           2'b10 : wb_sel_o <= 4'b0010;
+           2'b11 : wb_sel_o <= 4'b0001;
+         endcase // case(ram_addr[1:0])
+       end // if (ram_we)
+     else if(wb_ack_i)
+       wb_we_o <= 1'b0;
+      
 endmodule // ram_loader

Modified: gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_control.v  
2007-04-27 06:12:38 UTC (rev 5147)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_control.v  
2007-04-27 06:15:20 UTC (rev 5148)
@@ -4,26 +4,60 @@
 // DSP clock is the main system clock, at 100 MHz
 // It would be nice if WB_CLK could be 100 MHz, but it may
 // have to run at 1/2 rate (50 MHz) for cycle time reasons
+//
+// System bootup order:
+//    0 - Internal POR to reset this block.  Maybe control it from CPLD in the 
future?
+//    1 - Everything in reset, wb_clk from aux_clk
+//    2 - Take RAM Loader and wishbone out of reset
+//    3 - When RAM Loader done, take processor out of reset
+//    4 - When processor signals that it has set up the AD9510 properly,
+//               cut over to the wb_clk derived from (1/2 speed) main fpga 
clock
+//    5 - Optionally, somehow tell the CPLD to turn off the AUX clock
+//
+//   FIXME  Do we want to gate the DSP clock?
 
-module system_control (input aux_clk,
-                      input clk_fpga,
-                      input POR,
-                      
-                      output dsp_clk,
-                      output reset_out,
-                      output wb_clk_o,
-                      output reg wb_rst_o,
-                      output reg wb_rst_o_alt,
-                      
-                      output reg start,
-                      input done);
+module system_control 
+  (
+   // Input Clocks
+   input aux_clk_i,
+   input clk_fpga_i,
    
-   assign                    dsp_clk = clk_fpga;
-   assign                    reset_out = POR;
-   reg                               started, finished;
+   //Input Resets
+   // None for now, maybe take POR from CPLD later
+   
+   // Output clocks
+   output dsp_clk_o,
+   output wb_clk_o,
+   
+   // Output Resets
+   output ram_loader_rst_o,
+   output reg processor_rst_o,
+   output reg wb_rst_o,
+   output reg dsp_rst_o,
 
+   // Control inputs
+   input ram_loader_done_i,
+   input clock_ready_i,
+   
+   // Debug outputs
+   output [7:0] debug_o
+   );
+
+   reg                 POR;
+   reg [3:0]   POR_ctr;
+   initial POR = 1'b0;
+   initial #1 POR = 1'b1;
+   initial POR_ctr = 4'd0;
+   always @(posedge aux_clk_i)
+     if(POR_ctr == 4'd15)
+       POR <= 1'b0;
+     else
+       POR_ctr <= POR_ctr + 4'd1;
+   
+   reg                              start, started, finished;
+
    // Control the resets and start the initial programming of the clocks
-   always @(posedge POR or posedge aux_clk)
+   always @(posedge POR or posedge aux_clk_i)
      if(POR)
        begin
          wb_rst_o <= 1'b1;
@@ -40,40 +74,59 @@
          started <= #1 1'b1;
          start <= #1 1'b1;
        end
-     else if(done)
+     else if(clock_ready_i)
        finished <= #1 1'b1;
 
-   // Control the clocks
-   reg fin_ret_fpga, fin_ret_aux;  // Retimed finish signals
+   assign ram_loader_rst_o = wb_rst_o;
 
-   always @(posedge POR or negedge clk_fpga)
+   //  Processor Reset
+   always @(posedge POR or posedge wb_clk_o)
      if(POR)
-       fin_ret_fpga <= #1 1'b0;
+       processor_rst_o <= 1'b1;
+     else if(ram_loader_done_i)
+       processor_rst_o <= 1'b0;
+   
+   ////////////////////////////////////////////////////////////
+   //  Control the clocks
+   reg fin_ret_half, fin_ret_aux;  // Retimed finish signals
+
+   // Generate dsp_clk
+   reg clock_ready_ret, gate_dsp_clk, half_clk;
+   always @(posedge clk_fpga_i or posedge POR)
+     if(POR)
+       clock_ready_ret <= 1'b0;
      else
-       fin_ret_fpga <= #1 fin_ret_aux;
+       clock_ready_ret <= clock_ready_i;
 
-   always @(posedge POR or negedge aux_clk)
+   always @(negedge clk_fpga_i or posedge POR)
      if(POR)
+       gate_dsp_clk <= 1'b0;
+     else
+       gate_dsp_clk <= clock_ready_ret;
+   
+   assign dsp_clk_o = gate_dsp_clk & clk_fpga_i;
+
+   // Generate half frequency clock
+   always @(posedge POR or posedge clk_fpga_i)
+     if(POR)
+       half_clk <= 1'b0;
+     else
+       half_clk <= ~half_clk;
+   
+   always @(posedge POR or negedge half_clk)
+     if(POR)
+       fin_ret_half <= #1 1'b0;
+     else
+       fin_ret_half <= #1 fin_ret_aux;
+   
+   always @(posedge POR or negedge aux_clk_i)
+     if(POR)
        fin_ret_aux <= #1 1'b0;
      else   
        fin_ret_aux <= #1 finished;
    
-   assign wb_clk_o = (clk_fpga & fin_ret_fpga) | (aux_clk & ~fin_ret_aux);
-
-   reg           fin_del1, fin_del2, fin_del3;
+   assign wb_clk_o = (half_clk & fin_ret_half) | (aux_clk_i & ~fin_ret_aux);
    
-   always @(posedge wb_clk_o)
-     begin
-       fin_del1 <= #1 fin_ret_fpga;
-       fin_del2 <= #1 fin_del1;
-       fin_del3 <= #1 fin_del2;
-     end
-   
-   always @(posedge POR or posedge wb_clk_o)
-     if(POR)
-       wb_rst_o_alt <= #1 1'b1;
-     else if(fin_del3)
-       wb_rst_o_alt <= #1 1'b0;
-      
 endmodule // system_control
 
+

Added: gnuradio/branches/developers/matt/u2f/control_lib/system_control_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_control_tb.v       
                        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_control_tb.v       
2007-04-27 06:15:20 UTC (rev 5148)
@@ -0,0 +1,57 @@
+
+
+module system_control_tb();
+   
+   reg         aux_clk, clk_fpga;
+   wire wb_clk, dsp_clk;
+   wire wb_rst, dsp_rst, rl_rst, proc_rst;
+
+   reg         rl_done, clock_ready;
+   
+   initial aux_clk = 1'b0;
+   always #25 aux_clk = ~aux_clk;
+
+   initial clk_fpga = 1'b0;
+
+   initial clock_ready = 1'b0;
+   initial
+     begin
+       @(negedge proc_rst);
+       #1003 clock_ready <= 1'b1;
+     end
+
+   always #7 clk_fpga = ~clk_fpga;
+      
+   initial begin
+      $dumpfile("system_control_tb.vcd");
+      $dumpvars(0,system_control_tb);
+   end
+
+   initial #10000 $finish;
+
+   initial
+     begin
+       @(negedge rl_rst);
+       rl_done <= 1'b0;
+       #1325 rl_done <= 1'b1;
+     end
+
+   initial
+     begin
+       @(negedge proc_rst);
+       clock_ready <= 1'b0;
+       #327 clock_ready <= 1'b1;
+     end
+     
+   system_control 
+     system_control(.aux_clk_i(aux_clk),.clk_fpga_i(clk_fpga),
+                   .dsp_clk_o(dsp_clk),.wb_clk_o(wb_clk),
+                   .ram_loader_rst_o(rl_rst),
+                   .processor_rst_o(proc_rst),
+                   .wb_rst_o(wb_rst),
+                   .dsp_rst_o(dsp_rst),
+                   .ram_loader_done_i(rl_done),
+                   .clock_ready_i(clock_ready),
+                   .debug_o());
+   
+endmodule // system_control_tb