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[Commit-gnuradio] r5151 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5151 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sw/CVS sw/c |
|
Date: |
Fri, 27 Apr 2007 00:20:01 -0600 (MDT) |
Author: matt
Date: 2007-04-27 00:20:01 -0600 (Fri, 27 Apr 2007)
New Revision: 5151
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/endian-test.c
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
Log:
latest from opencores
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-27 06:18:23 UTC (rev 5150)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-27 06:20:01 UTC (rev 5151)
@@ -3,7 +3,7 @@
/aeMB_aslu.v/1.7/Fri Apr 27 01:14:55 2007//
/aeMB_control.v/1.4/Fri Apr 27 01:14:55 2007//
/aeMB_core.v/1.5/Fri Apr 27 01:14:55 2007//
-/aeMB_decode.v/1.6/Fri Apr 27 01:14:55 2007//
/aeMB_fetch.v/1.4/Fri Apr 27 01:14:55 2007//
-/aeMB_regfile.v/1.12/Fri Apr 27 01:14:56 2007//
+/aeMB_decode.v/1.7/Fri Apr 27 02:01:26 2007//
+/aeMB_regfile.v/1.13/Fri Apr 27 02:01:26 2007//
D
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-27 06:18:23 UTC (rev 5150)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-27 06:20:01 UTC (rev 5151)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_decode.v,v 1.6 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_decode.v,v 1.7 2007/04/27 04:23:17 sybreon Exp $
*
* AEMB Instruction Decoder
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -24,6 +24,9 @@
*
* HISTORY
* $Log: aeMB_decode.v,v $
+ * Revision 1.7 2007/04/27 04:23:17 sybreon
+ * Removed some unnecessary bubble control.
+ *
* Revision 1.6 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -174,19 +177,13 @@
*/
reg [1:0] rMXALU, xMXALU;
- always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT or frun)
- if (frun) begin
- xMXALU <= //(!fNBR) ? 2'o0 :
- (fSHIFT) ? 2'o2 :
- (fLOGIC) ? 2'o1 :
- (fBRA) ? 2'o3 :
- 2'o0;
- end else begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xMXALU <= 2'h0;
- // End of automatics
- end // else: !if(frun)
+ always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT) begin // frun
+ xMXALU <= //(!fNBR) ? 2'o0 :
+ (fSHIFT) ? 2'o2 :
+ (fLOGIC) ? 2'o1 :
+ (fBRA) ? 2'o3 :
+ 2'o0;
+ end
/**
BCC/BRA/RET
@@ -209,16 +206,18 @@
(fRET) ? 1'b1 :
(fBRU) ? wRA[4] :
1'b0;
- xMXLNK <= //(!fNBR) ? 1'b0 :
- (fBRU) ? wRA[2] : 1'b0;
end else begin // if (frun)
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
xMXBRA <= 2'h0;
xMXDLY <= 1'h0;
- xMXLNK <= 1'h0;
// End of automatics
end // else: !if(frun)
+
+ always @(/*AUTOSENSE*/fBRU or wRA) begin
+ xMXLNK <= //(!fNBR) ? 1'b0 :
+ (fBRU) ? wRA[2] : 1'b0;
+ end
/**
LD/ST
@@ -235,7 +234,7 @@
(fST) ? 2'o3 :
2'o0;
end else begin
- /*AUTORESET*/
+ /*UTORESET*/
// Beginning of autoreset for uninitialized flops
xMXLDST <= 2'h0;
// End of automatics
@@ -245,39 +244,31 @@
SRC/TGT
-------
Controls the muxes that select the appropriate sources for the A,
- B and D operands. All data hazards are resolved here.
+ B and D operands. All data hazards are resolved here.
*/
reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
- wire fRWE = (rRD != 5'd0) & (rMXBRA != 2'o3);
+ wire fRWE = (|rRD) & !(&rMXBRA);
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or rMXLDST or rRD
+ or wOPC or wRA or wRB) begin // frun
+ xMXSRC <= //(!fNBR) ? 2'o0 :
+ (fBRU|fBCC) ? 2'o1 : // PC
+ ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RA
+ xMXTGT <= //(!fNBR) ? 2'o0 :
+ (wOPC[3]) ? 2'o1 : // IMM
+ ((rRD == wRB) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRB) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RB
+ xMXALT <= //(!fNBR) ? 2'o0 :
+ //(fBRU|fBCC) ? 2'o1 : // PC
+ ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RA
+ end // always @ (...
- always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or frun or rMXLDST
- or rRD or wOPC or wRA or wRB)
- if (frun) begin
- xMXSRC <= //(!fNBR) ? 2'o0 :
- (fBRU|fBCC) ? 2'o1 : // PC
- ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
- ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
- 2'o0; // RA
- xMXTGT <= //(!fNBR) ? 2'o0 :
- (wOPC[3]) ? 2'o1 : // IMM
- ((rRD == wRB) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
- ((rRD == wRB) & fRWE) ? 2'o2 : // FWD
- 2'o0; // RB
- xMXALT <= //(!fNBR) ? 2'o0 :
- //(fBRU|fBCC) ? 2'o1 : // PC
- ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
- ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
- 2'o0; // RA
- end else begin // if (frun)
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xMXALT <= 2'h0;
- xMXSRC <= 2'h0;
- xMXTGT <= 2'h0;
- // End of automatics
- end // else: !if(frun)
-
/**
IMM Latching
------------
@@ -288,21 +279,13 @@
reg [31:0] rSIMM, xSIMM;
reg [15:0] rIMMHI, xIMMHI;
reg rFIMM, xFIMM;
-
- always @(/*AUTOSENSE*/fIMM or frun or rFIMM or rIMMHI or wIMM)
- if (frun) begin
- xSIMM <= (rFIMM) ? {rIMMHI,wIMM} : {{(16){wIMM[15]}},wIMM};
- xFIMM <= fIMM;
- xIMMHI <= (fIMM) ? wIMM : rIMMHI;
- end else begin
- /*AUTORESET*/
- // Beginning of autoreset for uninitialized flops
- xFIMM <= 1'h0;
- xIMMHI <= 16'h0;
- xSIMM <= 32'h0;
- // End of automatics
- end // else: !if(frun)
+ always @(/*AUTOSENSE*/fIMM or rFIMM or rIMMHI or wIMM) begin // frun
+ xSIMM <= (rFIMM) ? {rIMMHI,wIMM} : {{(16){wIMM[15]}},wIMM};
+ xFIMM <= fIMM;
+ xIMMHI <= (fIMM) ? wIMM : rIMMHI;
+ end
+
/**
COMPARATOR
----------
@@ -377,6 +360,7 @@
This signal controls the flag that determines whether a D register
is open for writing.
*/
+
reg rRWE, xRWE;
wire wRWE = |rRD;
always @(/*AUTOSENSE*/drun or rMXBRA or rMXLDST or wRWE)
@@ -420,7 +404,7 @@
always @(negedge nclk or negedge nrst)
if (!nrst) begin
- rOPC <= 6'o40;
+ //rOPC <= 6'o40;
/*AUTORESET*/
// Beginning of autoreset for uninitialized flops
rBRA <= 1'h0;
@@ -439,6 +423,7 @@
rMXLNK <= 1'h0;
rMXSRC <= 2'h0;
rMXTGT <= 2'h0;
+ rOPC <= 6'h0;
rRA <= 5'h0;
rRB <= 5'h0;
rRD <= 5'h0;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-27 06:18:23 UTC (rev 5150)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-27 06:20:01 UTC (rev 5151)
@@ -1,5 +1,5 @@
/*
- * $Id: aeMB_regfile.v,v 1.12 2007/04/27 00:23:55 sybreon Exp $
+ * $Id: aeMB_regfile.v,v 1.13 2007/04/27 04:22:40 sybreon Exp $
*
* AEMB Register File
* Copyright (C) 2004-2007 Shawn Tan Ser Ngiap <address@hidden>
@@ -27,6 +27,9 @@
*
* HISTORY
* $Log: aeMB_regfile.v,v $
+ * Revision 1.13 2007/04/27 04:22:40 sybreon
+ * Fixed minor synthesis bug.
+ *
* Revision 1.12 2007/04/27 00:23:55 sybreon
* Added code documentation.
* Improved size & speed of rtl/verilog/aeMB_aslu.v
@@ -75,9 +78,9 @@
dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRESULT, rFSM, rPC,
rOPC, rDWBSEL, rLNK, rRWE, nclk, nrst, drun, nrun
);
- // Data WB address bus width
+ // FIXME: This parameter is not used here.
parameter DSIZ = 32;
-
+
// Data WB Signals
output [31:0] dwb_dat_o;
input [31:0] dwb_dat_i;
@@ -95,15 +98,6 @@
input rLNK, rRWE;
input nclk, nrst, drun, nrun;
- // ASYNCHRONOUS
////////////////////////////////////////////////////////////////////
-
- wire [31:0] wRESULT;
- wire fWE = rRWE & !rDWBWE;
- wire fLNK = rLNK;
- wire fLD = rDWBSTB ^ rDWBWE;
- wire fDFWD = !(rRD ^ rRD_) & fWE;
- wire fMFWD = rDWBSTB & !rDWBWE;
-
/**
Delay Latches
----------
@@ -120,7 +114,20 @@
xPC_ <= rPC[31:2];
xRD_ <= rRD;
end
+
+ /**
+ Control Flags
+ -------------
+ Various internal flags.
+ */
+ wire [31:0] wRESULT;
+ wire fWE = rRWE & !rDWBWE;
+ wire fLNK = rLNK;
+ wire fLD = rDWBSTB ^ rDWBWE;
+ wire fDFWD = !(rRD ^ rRD_) & fWE;
+ wire fMFWD = rDWBSTB & !rDWBWE;
+
/**
Data WISHBONE Bus
-----------------
@@ -220,6 +227,7 @@
The register file is initialised with random values to reflect a
realistic situation where the values are undefined at power-up.
*/
+ // synopsys translate_off
integer i;
initial begin
for (i=0;i<31;i=i+1) begin
@@ -228,6 +236,7 @@
rMEMD[i] <= $random;
end
end
+ // synopsys translate_on
endmodule // aeMB_regfile
Modified: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-27 06:18:23 UTC (rev 5150)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-27 06:20:01 UTC (rev 5151)
@@ -1,2 +1,2 @@
D/c////
-/gccrom/1.3/Wed Apr 25 19:45:17 2007//
+/gccrom/1.3/Fri Apr 27 01:14:46 2007//
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/endian-test.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/endian-test.c
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/endian-test.c
2007-04-27 06:20:01 UTC (rev 5151)
@@ -0,0 +1,86 @@
+
+#include "memory_map.h"
+
+int main() {
+ char *p = (char *)0x4000;
+ short *q = (short *)0x5000;
+ int *r= (int *)0x6000;
+
+ int *output = (int *)0x7000;
+
+ char s;
+ short t;
+ int u;
+
+ // Write
+ // Bytes
+ *p = (char)1;
+ p++;
+ *p = (char)2;
+ p++;
+ *p = (char)3;
+ p++;
+ *p = (char)4;
+ p++;
+ *p = (char)5;
+
+ // Words
+ *q = (short) 0x1112;
+ q++;
+ *q = (short) 0x1314;
+ q++;
+ *q = (short) 0x1516;
+
+ // Double Words
+ *r = 0x21222324;
+ r++;
+ *r = 0x25262728;
+ r++;
+ *r = 0x292a2b2c;
+
+
+ // Read
+ p = (char *)0x6000;
+ s = *p;
+ if(s == 0x21)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+ p = (char *)0x6001;
+ s = *p;
+ if(s == 0x22)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+ p = (char *)0x6002;
+ s = *p;
+ if(s == 0x23)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+
+ p = (char *)0x6003;
+ s = *p;
+ if(s == 0x24)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+ q = (short *)0x4000;
+ t = *q;
+ if(t == 0x0102)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+ r = (int *)0x4000;
+ u = *r;
+ if(u == 0x01020304)
+ *output = 0x53534150; // PASS
+ else
+ *output = 0x4C494146; // FAIL
+
+}
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- [Commit-gnuradio] r5151 - in gnuradio/branches/developers/matt/u2f/opencores/aemb: rtl/verilog rtl/verilog/CVS sw/CVS sw/c,
matt <=