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[Commit-gnuradio] r5160 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5160 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells simulations |
|
Date: |
Fri, 27 Apr 2007 15:02:24 -0600 (MDT) |
Author: thottelt
Date: 2007-04-27 15:02:24 -0600 (Fri, 27 Apr 2007)
New Revision: 5160
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
Log:
make fifo_512 32 bits wide, broke channel reader/fifo and fake_fx2
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-27 20:37:55 UTC (rev 5159)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-27 21:02:24 UTC (rev 5160)
@@ -5,16 +5,17 @@
/* Module parameters */
parameter LOG2_N = 2 ;
- parameter WIDTH = 16 ;
+ parameter BUS_WIDTH = 16 ;
+ parameter FIFO_WIDTH = 32 ;
input wire reset;
input wire usb_clock ;
input wire fpga_clock ;
input wire write_enable ;
- input wire [WIDTH-1:0] write_data ;
+ input wire [BUS_WIDTH-1:0] write_data ;
input wire read_enable ;
input wire skip_packet ;
- output wire [WIDTH-1:0] read_data ;
+ output wire [FIFO_WIDTH-1:0] read_data ;
output wire have_space ;
output wire pkt_waiting ;
output wire tx_empty;
@@ -25,10 +26,10 @@
/* Local wires for FIFO connections */
wire [2**LOG2_N-1:0] fifo_resets ;
- wire [2**LOG2_N-1:0] fifo_we ;
+ reg [2**LOG2_N-1:0] fifo_we ;
wire [2**LOG2_N-1:0] fifo_re ;
- wire [WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ;
- wire [WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ;
+ reg [FIFO_WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ;
+ wire [FIFO_WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ;
wire [2**LOG2_N-1:0] fifo_rempty ;
wire [2**LOG2_N-1:0] fifo_rfull ;
wire [2**LOG2_N-1:0] fifo_wempty ;
@@ -38,6 +39,10 @@
reg [LOG2_N-1:0] fifo_rselect ;
reg [LOG2_N-1:0] fifo_wselect ;
+ /* Used to convert 16 bits usbdata to the 32 bits wide fifo */
+ reg second_half ;
+ reg [BUS_WIDTH-1:0] msb_usbdata ;
+
/* Assign have_space to empty flag of currently selected write FIFO */
assign have_space = fifo_wempty[fifo_wselect] ;
@@ -63,24 +68,42 @@
fifo_rselect <= fifo_rselect + 1 ;
end
- /* Increment fifo_wselect here */
+ /* Increment fifo_wselect and pack data into 32 bits block */
always @(posedge usb_clock, reset)
begin
if (reset)
+ begin
fifo_wselect <= {2**LOG2_N{1'b0}} ;
+ fifo_we <= {2**LOG2_N{1'b0}} ;
+ second_half <= 0;
+ end
if (fifo_wfull[fifo_wselect])
fifo_wselect <= fifo_wselect + 1 ;
+
+ if (write_enable)
+ if (second_half)
+ begin
+ fifo_wdata[fifo_wselect] <= {msb_usbdata, write_data} ;
+ fifo_we[fifo_wselect] <= 1 ;
+ second_half <= 0 ;
+ end
+ else
+ begin
+ msb_usbdata <= write_data ;
+ fifo_we[fifo_wselect] <= 0 ;
+ second_half <= 1 ;
+ end
+ else
+ fifo_we[fifo_wselect] <= 0 ;
end
/* Generate all the single packet FIFOs */
generate
for( i = 0 ; i < 2**LOG2_N ; i = i + 1 )
begin : generate_single_packet_fifos
- assign fifo_we[i] = (fifo_wselect == i) ? write_enable : 1'b0 ;
assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ;
assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ;
- assign fifo_wdata[i] = write_data ;
fifo_512 single_packet_fifo(.wrclk ( usb_clock ),
.rdclk ( fpga_clock ),
.aclr ( fifo_resets[i] ),
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
2007-04-27 20:37:55 UTC (rev 5159)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.bsf
2007-04-27 21:02:24 UTC (rev 5160)
@@ -26,8 +26,8 @@
(port
(pt 0 32)
(input)
- (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
- (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
@@ -82,8 +82,8 @@
(port
(pt 160 96)
(output)
- (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
- (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(port
@@ -101,7 +101,7 @@
(line (pt 160 136)(pt 144 136)(line_width 1))
)
(drawing
- (text "16 bits x 256 words" (rect 63 156 144 168)(font "Arial"
))
+ (text "32 bits x 128 words" (rect 63 156 144 168)(font "Arial"
))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 168)(line_width 1))
(line (pt 144 168)(pt 16 168)(line_width 1))
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
2007-04-27 20:37:55 UTC (rev 5159)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.cmp
2007-04-27 21:02:24 UTC (rev 5160)
@@ -17,12 +17,12 @@
PORT
(
aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
rdfull : OUT STD_LOGIC ;
wrempty : OUT STD_LOGIC ;
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
2007-04-27 20:37:55 UTC (rev 5159)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.inc
2007-04-27 21:02:24 UTC (rev 5160)
@@ -16,7 +16,7 @@
FUNCTION fifo_512
(
aclr,
- data[15..0],
+ data[31..0],
rdclk,
rdreq,
wrclk,
@@ -24,7 +24,7 @@
)
RETURNS (
- q[15..0],
+ q[31..0],
rdempty,
rdfull,
wrempty,
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
2007-04-27 20:37:55 UTC (rev 5159)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512.v
2007-04-27 21:02:24 UTC (rev 5160)
@@ -47,12 +47,12 @@
wrfull);
input aclr;
- input [15:0] data;
+ input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [15:0] q;
+ output [31:0] q;
output rdempty;
output rdfull;
output wrempty;
@@ -62,12 +62,12 @@
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
- wire [15:0] sub_wire4;
+ wire [31:0] sub_wire4;
wire rdfull = sub_wire0;
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
wire wrempty = sub_wire3;
- wire [15:0] q = sub_wire4[15:0];
+ wire [31:0] q = sub_wire4[31:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
@@ -92,11 +92,11 @@
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
- dcfifo_component.lpm_numwords = 256,
+ dcfifo_component.lpm_numwords = 128,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
- dcfifo_component.lpm_width = 16,
- dcfifo_component.lpm_widthu = 8,
+ dcfifo_component.lpm_width = 32,
+ dcfifo_component.lpm_widthu = 7,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON";
@@ -113,7 +113,7 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -125,7 +125,7 @@
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
@@ -139,17 +139,17 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
@@ -158,8 +158,8 @@
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
2007-04-27 20:37:55 UTC (rev 5159)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/megacells/fifo_512_bb.v
2007-04-27 21:02:24 UTC (rev 5160)
@@ -42,12 +42,12 @@
wrfull);
input aclr;
- input [15:0] data;
+ input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [15:0] q;
+ output [31:0] q;
output rdempty;
output rdfull;
output wrempty;
@@ -64,7 +64,7 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "128"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
@@ -76,7 +76,7 @@
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "1"
@@ -90,17 +90,17 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull
@@ -109,8 +109,8 @@
// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
-// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-04-27 20:37:55 UTC (rev 5159)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-04-27 21:02:24 UTC (rev 5160)
@@ -8,6 +8,12 @@
reg [15:0] usbdata;
reg WR;
+reg [100:0]line;
+reg [7:0]x1;
+reg [7:0]x2;
+reg [7:0]x3;
+reg [7:0]x4;
+
wire have_space;
fake_fx2_test fake_tx_buffer(
@@ -19,7 +25,7 @@
);
initial begin
- file = $fopen("4packets.dat", "r");
+ file = $fopen("packets.txt", "r");
start = 0;
count = 0;
usbclock = 0;
@@ -31,14 +37,18 @@
if (file == 0)
begin
- $display("cannot open packets.dat");
+ $display("cannot open packet.txt");
$finish;
end
while($feof(file) == 0)
begin
i = 0;
- r = $fread(packet, file);
+
+
+ r = $fscanf(file, "%x %x %x %x", x1, x2, x3, x4);
+
+ /*r = $fread(packet, file);
if (r != 512)
begin
$display("error while reading packets.dat");
@@ -58,7 +68,7 @@
usbdata = packet[i];
i = i + 1 ;
end
- WR = 0;
+ WR = 0;*/
end
$fclose(file);
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-27
20:37:55 UTC (rev 5159)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-27
21:02:24 UTC (rev 5160)
@@ -247,13 +247,13 @@
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ./usb_packet_fifo2_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177616757 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707359 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = ./fake_fx2_test.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = ./fake_fx2.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177517843 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 1
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177628865 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707346 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
@@ -275,7 +275,7 @@
Project_File_14 = ./usb_fifo_reader_test.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = ../inband/usrp/fpga/megacells/fifo_512.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177536644 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177705117 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -305,6 +305,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/fake_fx2.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
{Z:/wc/simulations/strobe_gen_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 0} {Z:/wc/usb_packet_fifo2.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 0 1}
+EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
{Z:/wc/simulations/strobe_gen_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 0}
{Z:/wc/simulations/fake_fx2_test.v 0 0}
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0} {Z:/wc/simulations/fake_fx2.v 0
1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-27 20:37:55 UTC (rev 5159)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-27 21:02:24 UTC (rev 5160)
@@ -10,7 +10,7 @@
reg [15:0]write_data ;
//Ouputs
- wire [15:0]read_data ;
+ wire [31:0]read_data ;
wire have_space ;
wire tx_empty ;
wire pkt_waiting ;
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- [Commit-gnuradio] r5160 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/megacells simulations,
thottelt <=