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[Commit-gnuradio] r5165 - in gnuradio/branches/developers/thottelt: inba
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From: |
thottelt |
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Subject: |
[Commit-gnuradio] r5165 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations |
|
Date: |
Fri, 27 Apr 2007 18:15:11 -0600 (MDT) |
Author: thottelt
Date: 2007-04-27 18:15:11 -0600 (Fri, 27 Apr 2007)
New Revision: 5165
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
Log:
everything's broken :(
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-04-27 23:38:20 UTC (rev 5164)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-04-28 00:15:11 UTC (rev 5165)
@@ -1,152 +1,134 @@
-module usb_fifo_reader (
- input tx_clock,
- input [15:0] fifodata,
- input pkt_waiting,
- input reset,
- output reg rdreq,
- output reg skip,
- output reg cmd_done,
- output reg chan_0_done,
- output reg chan_1_done,
- output reg WR_cmd,
- output reg WR_chan_0,
- output reg WR_chan_1,
- output reg [15:0] tx_data_bus) ;
+module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
+ rdreq, skip, done_chan, WR_chan, tx_data_bus);
+
+ /* Module parameters */
+ parameter NUM_CHAN = 2 ;
+ parameter WIDTH = 32 ;
+
+ input wire tx_clock ;
+ input wire reset ;
+ input wire [WIDTH-1:0] fifodata ;
+ input wire pkt_waiting ;
+ output reg rdreq ;
+ output reg skip ;
+ output reg [NUM_CHAN:0] done_chan ;
+ output reg [NUM_CHAN:0] WR_chan ;
+ output reg [WIDTH-1:0] tx_data_bus ;
+
- // States
- `define IDLE 3'd0
- `define WAIT 3'd1
- `define READ_TARGET 3'd2
- `define READ_LENGTH 3'd3
- `define FORWARD_DATA 3'd4
- `define SKIP_REST 3'd5
- `define TXCHAN0 5'h0
- `define TXCHAN1 5'h1
- `define TXCMD 5'h1F
+ /* States definition */
+ `define IDLE 3'd0
+ `define WAIT 3'd1
+ `define READ_HEADER 3'd2
+ `define FORWARD_DATA 3'd3
+ `define SKIP_REST 3'd4
- reg [2:0] reader_state;
- reg [2:0] reader_next_state;
- reg [4:0] channel;
- reg [8:0] pkt_length;
- reg [8:0] read_length;
+ /* Channel Ids */
+ `define TXCHAN0 5'h0
+ `define TXCHAN1 5'h1
+ `define TXCMD 5'h1F
+
+ /* Local registers */
+ reg [2:0] reader_state ;
+ reg [2:0] reader_next_state ;
+ reg [4:0] channel ;
+ reg [8:0] pkt_length ;
+ reg [8:0] read_length ;
- // FSM
+ /* State Machine */
always @(posedge tx_clock)
begin
if (reset)
begin
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- rdreq <= 0;
- skip <= 0;
- WR_chan_0 <= 0;
- WR_chan_1 <= 0;
- WR_cmd <= 0;
+ reader_state <= `IDLE ;
+ reader_next_state <= `IDLE ;
+ rdreq <= 0 ;
+ skip <= 0 ;
+ WR_chan <= {NUM_CHAN+1{1'b0}} ;
+ done_chan <= {NUM_CHAN+1{1'b0}} ;
end
else
begin
- reader_state = reader_next_state;
+ reader_state = reader_next_state ;
+
case(reader_state)
- `IDLE:
+ `IDLE:
begin
- reader_next_state <= pkt_waiting ? `WAIT : `IDLE;
- rdreq <= pkt_waiting;
-
- // Unset the done flag from the previous
packet
- cmd_done <= 0;
- chan_1_done <= 0;
- chan_0_done <= 0;
- end
+ reader_next_state <= pkt_waiting ? `WAIT :
`IDLE ;
+ rdreq <= pkt_waiting ;
+ end
- // Wait for the fifo's data
- `WAIT:
- begin
- reader_next_state <= `READ_TARGET;
- end
+ /* Wait for the fifo's data to show up */
+ `WAIT:
+ begin
+ reader_next_state <= `READ_HEADER ;
+ end
- `READ_TARGET:
- begin
- reader_next_state <= `READ_LENGTH;
-
- // Unset the done flag from the previous
packet
- cmd_done <= 0;
- chan_1_done <= 0;
- chan_0_done <= 0;
+ `READ_HEADER:
+ begin
+ reader_next_state <= `FORWARD_DATA ;
- channel = (fifodata & 16'h1F);
+ /* Read header fields */
+ channel <= (fifodata & 32'h1F0000) ;
+ pkt_length <= (fifodata & 16'h1FF) + 4 ;
+ read_length <= 9'd0 ;
- // Forward data
- tx_data_bus <= fifodata;
- case (channel)
- `TXCHAN0: WR_chan_0 <= 1;
- `TXCHAN1: WR_chan_1 <= 1;
- `TXCMD: WR_cmd <= 1;
- //invalid channel -> channel 0;
- default: WR_chan_0 <= 1;
- endcase
- end
-
- `READ_LENGTH:
- begin
- reader_next_state <= `FORWARD_DATA;
-
- // Plus two bytes for timestamp
- pkt_length <= (fifodata & 16'h1FF) + 2;
- read_length <= 9'd0;
-
- // Forward data
- tx_data_bus <= fifodata;
- end
+ /* Forward data */
+ case (channel)
+ `TXCHAN0: WR_chan[0] <= 1 ;
+ `TXCHAN1: WR_chan[1] <= 1 ;
+ `TXCMD: WR_chan[2] <= 1 ;
+ default: WR_chan <= 1 ;
+ endcase
+ tx_data_bus <= fifodata ;
+ end
- `FORWARD_DATA:
- begin
- read_length <= read_length + 2;
+ `FORWARD_DATA:
+ begin
+ read_length <= read_length + 4 ;
- // If end of payload...
- if (read_length == pkt_length)
+ // If end of payload...
+ if (read_length == pkt_length)
begin
- reader_next_state <= `SKIP_REST;
- // If the packet is 512 bytes, don't skip
- skip <= pkt_length < 506;
- end
- else if (read_length == pkt_length - 2)
- rdreq <= 0;
+ reader_next_state <= `SKIP_REST ;
+ /* If the packet is 512 bytes, don't skip */
+ skip <= pkt_length < 506 ;
+
+ /* Data pushing done */
+ WR_chan <= {NUM_CHAN+1{1'b0}} ;
- // Forward data
- tx_data_bus <= fifodata;
+ /* Notify next block */
+ case (channel)
+ `TXCHAN0: done_chan[0] <= 1 ;
+ `TXCHAN1: done_chan[1] <= 1 ;
+ `TXCMD: done_chan[2] <= 1 ;
+ default: done_chan[0] <= 1 ;
+ endcase
end
+ else if (read_length == pkt_length - 4)
+ rdreq <= 0 ;
+
+ /* Forward data */
+ tx_data_bus <= fifodata ;
+ end
- `SKIP_REST:
- begin
- reader_next_state <= pkt_waiting ? `READ_TARGET : `IDLE;
-
- // Data pushing done
- WR_chan_0 <= 0;
- WR_chan_1 <= 0;
- WR_cmd <= 0;
-
- case (channel)
- `TXCHAN0: chan_0_done <= 1;
- `TXCHAN1: chan_0_done <= 1;
- `TXCMD: cmd_done <= 1;
- //invalid channel -> channel 0;
- default: WR_chan_0 <= 1;
- endcase
-
- rdreq <= pkt_waiting;
- skip <= 0;
- end
- // reset
- default:
- begin
- reader_state <= `IDLE;
- reader_next_state <= `IDLE;
- end
- endcase
+ `SKIP_REST:
+ begin
+ reader_next_state <= pkt_waiting ? `READ_HEADER
: `IDLE ;
+ done_chan <= {NUM_CHAN+1{1'b0}} ;
+ rdreq <= pkt_waiting ;
+ skip <= 0 ;
+ end
+
+ default:
+ begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
end
- end
-
+ end
endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-27 23:38:20 UTC (rev 5164)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
2007-04-28 00:15:11 UTC (rev 5165)
@@ -26,9 +26,9 @@
/* Local wires for FIFO connections */
wire [2**LOG2_N-1:0] fifo_resets ;
- reg [2**LOG2_N-1:0] fifo_we ;
+ wire [2**LOG2_N-1:0] fifo_we ;
wire [2**LOG2_N-1:0] fifo_re ;
- reg [FIFO_WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ;
+ wire [FIFO_WIDTH-1:0] fifo_wdata[2**LOG2_N-1:0] ;
wire [FIFO_WIDTH-1:0] fifo_rdata[2**LOG2_N-1:0] ;
wire [2**LOG2_N-1:0] fifo_rempty ;
wire [2**LOG2_N-1:0] fifo_rfull ;
@@ -74,28 +74,32 @@
if (reset)
begin
fifo_wselect <= {2**LOG2_N{1'b0}} ;
- fifo_we <= {2**LOG2_N{1'b0}} ;
+ //fifo_we <= {2**LOG2_N{1'b0}} ;
second_half <= 0;
end
if (fifo_wfull[fifo_wselect])
fifo_wselect <= fifo_wselect + 1 ;
- if (write_enable)
- if (second_half)
- begin
- fifo_wdata[fifo_wselect] <= {msb_usbdata, write_data} ;
- fifo_we[fifo_wselect] <= 1 ;
- second_half <= 0 ;
- end
- else
- begin
- msb_usbdata <= write_data ;
- fifo_we[fifo_wselect] <= 0 ;
- second_half <= 1 ;
- end
- else
- fifo_we[fifo_wselect] <= 0 ;
+ /*if (write_enable)
+ begin
+ if (second_half)
+ begin
+ fifo_wdata[fifo_wselect] <= {msb_usbdata, write_data} ;
+ fifo_we[fifo_wselect] <= 1 ;
+ second_half <= 0 ;
+ end
+ else
+ begin
+ msb_usbdata <= write_data ;
+ fifo_we[fifo_wselect] <= 0 ;
+ second_half <= 1 ;
+ end
+ end
+ else
+ begin
+ fifo_we[fifo_wselect] <= 0 ;
+ end*/
end
/* Generate all the single packet FIFOs */
@@ -104,6 +108,8 @@
begin : generate_single_packet_fifos
assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ;
assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ;
+ assign fifo_we[i] = (fifo_wselect == i) ? write_enable : 1'b0 ;
+ assign fifo_wdata[i] = write_data;
fifo_512 single_packet_fifo(.wrclk ( usb_clock ),
.rdclk ( fpga_clock ),
.aclr ( fifo_resets[i] ),
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-27
23:38:20 UTC (rev 5164)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-28
00:15:11 UTC (rev 5165)
@@ -247,15 +247,15 @@
Project_File_0 = ./strobe_gen_test.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = ./usb_packet_fifo2_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707359 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177718026 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = ./fake_fx2_test.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = ./fake_fx2.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177707346 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177718354 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272423 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 8
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177712049 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177273481 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
@@ -273,7 +273,7 @@
Project_File_13 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = ./usb_fifo_reader_test.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177272433 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177713127 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = ../inband/usrp/fpga/megacells/fifo_512.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177705117 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
@@ -305,6 +305,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_reader.v 0 0}
{Z:/wc/simulations/strobe_gen_test.v 0 0}
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0}
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 0}
{Z:/wc/simulations/fake_fx2_test.v 0 0}
{Z:/wc/simulations/usb_fifo_reader_test.v 0 0} {Z:/wc/simulations/fake_fx2.v 0
1}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/usb_packet_fifo2_test.v
0 0} {Z:/wc/simulations/fake_fx2.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 1
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-04-27 23:38:20 UTC (rev 5164)
+++ gnuradio/branches/developers/thottelt/simulations/usb_fifo_reader_test.v
2007-04-28 00:15:11 UTC (rev 5165)
@@ -8,38 +8,41 @@
reg reset;
//OUPUTS
-wire [15:0] tx_data_bus;
-wire WR_chan_0;
-wire WR_chan_1;
-wire WR_cmd;
+wire [31:0] tx_data_bus;
+wire [2:0]WR_chan;
+wire [2:0]done_chan;
+wire have_space ;
+wire tx_empty ;
+
reg [15:0] i ;
-wire [15:0] fifodata;
+wire [31:0] fifodata;
wire rdreq;
wire skip;
wire pkt_waiting;
// FIFO
- usb_packet_fifo tx_usb_fifo
- ( .reset(reset),
- .clock_in(usb_clock),
- .clock_out(tx_clock),
- .ram_data_in(usb_data),
- .write_enable(WR),
- .ram_data_out(fifodata),
- .pkt_waiting(pkt_waiting),
- .read_enable(rdreq),
- .skip_packet(skip)
- );
+ usb_packet_fifo2 usb_fifo (
+ .reset (reset),
+ .usb_clock (usb_clock),
+ .fpga_clock (tx_clock),
+ .have_space (have_space),
+ .pkt_waiting (pkt_waiting),
+ .tx_empty (tx_empty),
+ .write_enable (WR),
+ .read_enable (rdreq),
+ .skip_packet (skip),
+ .read_data (fifodata),
+ .write_data (usb_data)
+ ) ;
usb_fifo_reader reader (
.reset(reset),
.tx_clock(tx_clock),
.tx_data_bus(tx_data_bus),
- .WR_chan_0(WR_chan_0),
- .WR_chan_1(WR_chan_1),
- .WR_cmd(WR_cmd),
+ .WR_chan(WR_chan),
+ .done_chan(done_chan),
.fifodata(fifodata),
.pkt_waiting(pkt_waiting),
.rdreq(rdreq),
@@ -58,7 +61,7 @@
i = 0 ;
// Deassert the reset
- #40 reset = 1'b0 ;
+ #80 reset = 1'b0 ;
// Wait a few clocks
repeat (5) begin
@@ -77,8 +80,16 @@
usb_data = i ;
i = i + 1 ;
end
+ @(posedge usb_clock)
+ WR = 1'b0 ;
i = 0;
+ // Wait
+ while(have_space == 0)
+ begin
+ @(posedge usb_clock)
+ i = 0;
+ end
// Write one full packet (channel 1)
repeat (256) begin
@@ -94,8 +105,16 @@
usb_data = i ;
i = i + 1 ;
end
+ @(posedge usb_clock)
+ WR = 1'b0 ;
i = 0;
+ // Wait
+ while(have_space == 0)
+ begin
+ @(posedge usb_clock)
+ i = 0;
+ end
// Write one half full packet (cmd)
repeat (256) begin
@@ -111,7 +130,6 @@
usb_data = i ;
i = i + 1 ;
end
-
@(posedge usb_clock)
WR = 1'b0 ;
end
Modified:
gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-27 23:38:20 UTC (rev 5164)
+++ gnuradio/branches/developers/thottelt/simulations/usb_packet_fifo2_test.v
2007-04-28 00:15:11 UTC (rev 5165)
@@ -43,10 +43,12 @@
#40 reset = 1'b0 ;
// Wait a few clocks
- repeat (5) begin
+ repeat (6) begin
@(posedge usb_clock)
- reset = 1'b0 ;
+ skip_packet = 1;
end
+ @(posedge usb_clock)
+ skip_packet = 0;
// Write an entire packets worth of data
// into the FIFO
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- [Commit-gnuradio] r5165 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations,
thottelt <=