[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5633 - in gnuradio/branches/developers/thottelt: inba
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5633 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations |
|
Date: |
Sat, 2 Jun 2007 23:23:39 -0600 (MDT) |
Author: thottelt
Date: 2007-06-02 23:23:38 -0600 (Sat, 02 Jun 2007)
New Revision: 5633
Added:
gnuradio/branches/developers/thottelt/simulations/data_packet_fifo_test.v
gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
Fix endianess bugs
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-03 05:20:22 UTC (rev 5632)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -98,14 +98,14 @@
tx_empty <= 1 ;
//Check Start/End burst flag
- if (fifodata[3] == 1 && fifodata[4] == 1)
+ if (fifodata[28] == 1 && fifodata[27] == 1)
burst <= 0;
- else if (fifodata[3] == 1)
+ else if (fifodata[28] == 1)
burst <= 1;
- else if (fifodata[4] == 1)
+ else if (fifodata[27] == 1)
burst <= 0;
- payload_len <= (fifodata & 16'h1FF) ;
+ payload_len <= fifodata[8:0] ;
read_len <= 0;
rdreq <= 0;
@@ -201,4 +201,4 @@
end
end
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-03 05:20:22 UTC (rev 5632)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -76,7 +76,7 @@
wire [15:0] tx_i [NUM_CHAN-1:0] ;
wire [15:0] tx_q [NUM_CHAN-1:0] ;
- assign have_space = (tupf_wrusedw <= 128) ;
+ assign have_space = (tupf_wrusedw < 127) ;
assign tupf_pkt_waiting = (tupf_rdusedw >= 128) ;
/* TODO: Figure out how to write this genericly */
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-03 05:20:22 UTC (rev 5632)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -71,7 +71,7 @@
begin
/* Read header fields */
channel <= (fifodata[20:16]) ;
- pkt_length <= (fifodata & 32'h1FF) + 8 ;
+ pkt_length <= fifodata[8:0] + 8 ;
read_length <= 10'd0 ;
if (have_space_chan[channel])
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-03 05:20:22 UTC (rev 5632)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -20,7 +20,8 @@
reg writing ;
- assign write_data = {write_data_delayed, bus_data} ;
+ //assign write_data = {write_data_delayed, bus_data} ;
+ assign write_data = {bus_data, write_data_delayed} ;
assign write_enable_fifo = ~word_complete & writing ;
always @(posedge usb_clock)
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-03 05:20:22 UTC (rev 5632)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2007-06-03 05:23:38 UTC (rev 5633)
@@ -31,10 +31,10 @@
// ====================================================================
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
- `include "../include/common_config_1rxhb_1tx.vh"
+//`include "../include/common_config_1rxhb_1tx.vh"
// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-//`include "../include/common_config_2rxhb_2tx.vh"
+ `include "../include/common_config_2rxhb_2tx.vh"
// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
//`include "../include/common_config_4rx_0tx.vh"
Modified:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_1_channel.dat
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/thottelt/simulations/all_valid_packet_lengths_2_channels.dat
===================================================================
(Binary files differ)
Added: gnuradio/branches/developers/thottelt/simulations/data_packet_fifo_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/data_packet_fifo_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/data_packet_fifo_test.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -0,0 +1,209 @@
+module data_packet_fifo_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [31:0] data_bus;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg pkt_complete;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire overrun;
+wire underrun;
+
+reg [15:0] i ;
+
+// fifo inputs
+reg skip;
+reg rdreq;
+
+// fifo ouputs
+wire [31:0] fifodata;
+wire pkt_waiting;
+wire tx_strobe;
+
+// Channel fifo
+ data_packet_fifo tx_data_fifo
+ ( .reset(reset),
+ .clock(txclock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip),
+ .have_space()
+ );
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ txclock = 0;
+ data_bus = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ pkt_complete = 0;
+ rdreq = 0;
+ skip = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (20) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+ // Payload len
+ if (i == 0)
+ data_bus = 32;
+ // First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1000;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+ @(posedge txclock)
+ WR <= 0;
+ @(posedge txclock)
+ WR <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+
+ repeat (128) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+ @(posedge txclock)
+ WR = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+
+ repeat (128) begin
+ @(posedge txclock)
+ rdreq = 1;
+ end
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ end
+
+always
+ #5 txclock = ~txclock ;
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/simulations/data_packet_fifo_test.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-03 05:20:22 UTC (rev 5632)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -2,7 +2,7 @@
integer file, start, count, r;
-reg [15:0] packet [255:0];
+reg [7:0] packet [0:511];
reg usbclock;
reg txclock;
reg reset;
@@ -22,6 +22,7 @@
wire [15:0]tx_q_2;
wire [15:0]tx_i_3;
wire [15:0]tx_q_3;
+wire ok;
/* NOT USED YET */
reg bus_reset;
@@ -61,9 +62,18 @@
.strobe(txstrobe) );
+fake_tx_chain tx_chain(
+ .reset(reset),
+ .tx_empty(tx_empty),
+ .txstrobe(txstrobe),
+ .tx_q(tx_q_0),
+ .tx_i(tx_i_0),
+ .ok(ok)
+ );
+
initial begin
- file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
- //file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
+ //file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
start = 0;
count = 0;
usbclock = 0;
@@ -92,8 +102,13 @@
if (r != 512)
begin
$display("error while reading packets.dat");
- $finish;
+ //$finish;
end
+ else if (r == 0)
+ begin
+ $display("Done reading packets.dat");
+ $finish;
+ end
// Wait
i = 0;
@@ -106,8 +121,8 @@
repeat (256) begin
@(posedge usbclock)
WR = 1;
- usbdata = packet[i];
- i = i + 1 ;
+ usbdata = {packet[2*i+1],packet[2*i]};
+ i = i + 1 ;
end
@(posedge usbclock)
WR = 0;
Added: gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
2007-06-03 05:23:38 UTC (rev 5633)
@@ -0,0 +1,43 @@
+module fake_tx_chain
+ ( reset, tx_empty, txstrobe, tx_q, tx_i, ok);
+
+ input wire reset ;
+ input wire tx_empty ;
+ input wire txstrobe ;
+ input wire [15:0] tx_q ;
+ input wire [15:0] tx_i ;
+ output reg ok ;
+
+ reg [15:0] counter ;
+
+ always @(reset)
+ begin
+ if (reset)
+ begin
+ ok = 1 ;
+ counter = 0 ;
+ end
+ end
+
+ always @(posedge txstrobe)
+ begin
+ if (tx_empty == 0)
+ begin
+ if (tx_q != counter)
+ begin
+ ok = 0 ;
+ $display("Q samples do not match");
+ //$finish;
+ end
+ if (tx_i != counter + 1)
+ begin
+ ok = 0 ;
+ $display("I samples do not match");
+ //$finish;
+ end
+
+ counter = counter + 2 ;
+ end
+ end
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/simulations/fake_tx_chain.v
___________________________________________________________________
Name: svn:executable
+ *
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-03
05:20:22 UTC (rev 5632)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-06-03
05:23:38 UTC (rev 5633)
@@ -243,41 +243,43 @@
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
-Project_Files_Count = 17
+Project_Files_Count = 18
Project_File_0 = ./strobe_gen_test.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = ./usb_fifo_writer_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234317 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = Z:/wc/simulations/data_packet_fifo_test.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178643008 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
16 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = ./fake_fx2_test.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177428969 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_4 = ./fake_fx2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015942 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
11 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178726590 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_6 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179010971 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015841 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178234886 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = ./chan_fifo_readers_test.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178644650 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015567 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = ./usb_packet_fifo_test.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232288 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = ./tx_buffer_test.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179008242 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1179015176 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_15 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178232291 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = ./usb_fifo_reader_test.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1178397904 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = Z:/wc/simulations/fake_tx_chain.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
17 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = ./fake_fx2_test.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
12 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = ./fake_fx2.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180848225 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_6 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180839053 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_7 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180839253 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 6
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180847316 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 4
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180832728 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_10 = ./chan_fifo_readers_test.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 1
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ./usb_packet_fifo_test.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_13 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 7
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = ./tx_buffer_test.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 5
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 9
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_17 = ./usb_fifo_reader_test.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -307,6 +309,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 1}
{Z:/wc/simulations/fake_fx2.v 0 0}
+EditorState = {tabbed horizontal 1} {Z:/wc/simulations/tx_buffer_test.v 0 0}
{Z:/wc/simulations/fake_fx2.v 0 1}
{Z:/wc/inband/usrp/fpga/inband_lib/usb_fifo_writer.v 0 0}
{Z:/wc/simulations/fake_tx_chain.v 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5633 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib inband/usrp/fpga/toplevel/usrp_inband_usb simulations,
thottelt <=