[Commit-gnuradio] r5728 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simulations

[thottelt]

Author: thottelt
Date: 2007-06-06 21:54:57 -0600 (Wed, 06 Jun 2007)
New Revision: 5728

Modified:
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
   
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
   gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
   gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
cross clock boundaries code messed up

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-06-07 02:27:17 UTC (rev 5727)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-06-07 03:54:57 UTC (rev 5728)
@@ -100,8 +100,8 @@
                    else if (fifodata[27] == 1)
                        burst <= 0;
                        
-                   payload_len <= fifodata[8:0] ;
-                                  //payload_len <= 9'd504 ;
+                   //payload_len <= fifodata[8:0] ;
+                                  payload_len <= 9'd504 ;
                    read_len <= 0;
                         
                    rdreq <= 0;

Modified: 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
--- 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
 2007-06-07 02:27:17 UTC (rev 5727)
+++ 
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
 2007-06-07 03:54:57 UTC (rev 5728)
@@ -75,39 +75,67 @@
     
    always @(posedge usbclk)
    begin
-       usbdata_usbclk <= usbdata_packed;
+       if (WR)
+          usbdata_usbclk <= usbdata_packed;
        WR_usbclk <= WR;
    end
 
        reg [FIFO_WIDTH-1:0] usbdata_tx ;
        reg WR_tx;
-   reg fresh;
-       
- always @(posedge txclk)
-    begin
-              if (reset)
-                         begin
-                               WR_tx <= 0;
-                               fresh <= 1;
-                         end
-                       else if (WR_usbclk & ~WR_tx & fresh)
-                         begin
-                               usbdata_tx <= usbdata_usbclk ;
-                               WR_tx <= 1 ;
-                         end
-                       else if (WR_usbclk & WR_tx)
-                         begin
-                          WR_tx <= 0;
-                          fresh <= 0;
-                         end
-                       else if (WR_tx)
-                         begin
-                          WR_tx <= 0;
-                          fresh <= 1;
-                         end
-                       else if (~WR_usbclk)
-                          fresh <= 1;
-               end
+   reg WR_1;
+   reg WR_2;
+   
+   always @(posedge txclk) 
+   if (reset)
+      WR_1 <= 0;
+   else
+      WR_1 <= WR_usbclk;
+   always @(posedge txclk) 
+   if (reset)
+      WR_2 <= 0;
+   else
+      WR_2 <= WR_1;
+   
+   always @(posedge txclk) usbdata_tx[0] <= usbdata_usbclk[0];
+   always @(posedge txclk) usbdata_tx[1] <= #1 usbdata_usbclk[1];
+   always @(posedge txclk) usbdata_tx[2] <= #2 usbdata_usbclk[2];
+   always @(posedge txclk) usbdata_tx[3] <= #3 usbdata_usbclk[3];
+   always @(posedge txclk) usbdata_tx[4] <= #4 usbdata_usbclk[4];
+   always @(posedge txclk) usbdata_tx[5] <= #5 usbdata_usbclk[5];
+   always @(posedge txclk) usbdata_tx[6] <= #6 usbdata_usbclk[6];
+   always @(posedge txclk) usbdata_tx[7] <= #7 usbdata_usbclk[7];
+   always @(posedge txclk) usbdata_tx[8] <= #8 usbdata_usbclk[8];
+   always @(posedge txclk) usbdata_tx[9] <= #9 usbdata_usbclk[9];
+   always @(posedge txclk) usbdata_tx[10] <= #10 usbdata_usbclk[10];
+   always @(posedge txclk) usbdata_tx[11] <= #11 usbdata_usbclk[11];
+   always @(posedge txclk) usbdata_tx[12] <= #12 usbdata_usbclk[12];
+   always @(posedge txclk) usbdata_tx[13] <= #13 usbdata_usbclk[13];
+   always @(posedge txclk) usbdata_tx[14] <= #14 usbdata_usbclk[14];
+   always @(posedge txclk) usbdata_tx[15] <= #15 usbdata_usbclk[15];
+   always @(posedge txclk) usbdata_tx[16] <= #16 usbdata_usbclk[16];
+   always @(posedge txclk) usbdata_tx[17] <= #17 usbdata_usbclk[17];
+   always @(posedge txclk) usbdata_tx[18] <= #18 usbdata_usbclk[18];
+   always @(posedge txclk) usbdata_tx[19] <= #19 usbdata_usbclk[19];
+   always @(posedge txclk) usbdata_tx[20] <= #20 usbdata_usbclk[20];
+   always @(posedge txclk) usbdata_tx[21] <= #21 usbdata_usbclk[21];
+   always @(posedge txclk) usbdata_tx[22] <= #22 usbdata_usbclk[22];
+   always @(posedge txclk) usbdata_tx[23] <= #23 usbdata_usbclk[23];
+   always @(posedge txclk) usbdata_tx[24] <= #1 usbdata_usbclk[24];
+   always @(posedge txclk) usbdata_tx[25] <= #2 usbdata_usbclk[25];
+   always @(posedge txclk) usbdata_tx[26] <= #3 usbdata_usbclk[26];
+   always @(posedge txclk) usbdata_tx[27] <= #4 usbdata_usbclk[27];
+   always @(posedge txclk) usbdata_tx[28] <= #5 usbdata_usbclk[28];
+   always @(posedge txclk) usbdata_tx[29] <= #6 usbdata_usbclk[29];
+   always @(posedge txclk) usbdata_tx[30] <= #7 usbdata_usbclk[30];
+   always @(posedge txclk) usbdata_tx[31] <= #8 usbdata_usbclk[31];
+
+       always @(posedge txclk)
+       begin
+               if (reset)
+                       WR_tx <= 0;
+               else
+                  WR_tx = WR_1 & ~WR_2;
+       end
        
        reg [3:0]reader_state;
        reg [4:0]channel ;

Modified: gnuradio/branches/developers/thottelt/simulations/fake_fx2.v
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/fake_fx2.v        
2007-06-07 02:27:17 UTC (rev 5727)
+++ gnuradio/branches/developers/thottelt/simulations/fake_fx2.v        
2007-06-07 03:54:57 UTC (rev 5728)
@@ -57,7 +57,7 @@
    .clock(txclock),
    .reset(reset),
    .enable(1'd1),
-   .rate(8'd3),
+   .rate(8'd6),
    .strobe_in(1'd1),
    .strobe(txstrobe) );
 
@@ -141,7 +141,7 @@
 end
 
 always
-   #63 usbclock = ~ usbclock;
+   #64 usbclock = ~ usbclock;
 always  
    #48 txclock = ~ txclock;
     

Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-06-07 
02:27:17 UTC (rev 5727)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf    2007-06-07 
03:54:57 UTC (rev 5728)
@@ -244,54 +244,54 @@
 Project_DefaultLib = work
 Project_SortMethod = unused
 Project_Files_Count = 24
-Project_File_0 = Z:/wc/simulations/fake_tx_chain.v
-Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_1 = ./chan_fifo_readers_test.v
-Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_2 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
-Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181169257 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
13 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_3 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
-Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
19 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_4 = ./usb_packet_fifo_test.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_5 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181008809 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_6 = ./tx_buffer_test.v
-Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_7 = Z:/wc/simulations/channel_ram_test.v
-Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181060194 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
23 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_8 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
-Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_9 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
-Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181058450 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 22 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_10 = Z:/wc/simulations/data_packet_fifo_test.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
16 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_11 = 
Z:/wc/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 21 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_12 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_13 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
-Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_14 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
20 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_15 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
18 dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_16 = ./fake_fx2_test.v
-Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_17 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_18 = ./usb_fifo_reader_test.v
-Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_19 = ./strobe_gen_test.v
-Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_20 = ./usb_fifo_writer_test.v
-Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181165989 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_21 = ./fake_fx2.v
-Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181165192 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 
cover_expr 0 dont_compile 0 cover_stmt 0
-Project_File_22 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
-Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181161472 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
-Project_File_23 = ../inband/usrp/fpga/megacells/fifo_1k.v
-Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_0 = ./strobe_gen_test.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 10 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = ./usb_fifo_writer_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181165989 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181182007 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
22 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_3 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
16 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = Z:/wc/simulations/fake_tx_chain.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180840688 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_5 = Z:/wc/inband/usrp/fpga/megacells/fifo_2k.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
18 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_6 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_chain.v
+Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726981 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_7 = ./fake_fx2_test.v
+Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_8 = 
Z:/wc/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
+Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 1 vlog_upper 0 compile_to work vlog_options {} compile_order 21 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_9 = ./fake_fx2.v
+Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181183422 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 11 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_10 = ../inband/usrp/fpga/inband_lib/chan_fifo_reader.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181182317 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 6 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_11 = ../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180995228 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 8 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_12 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181158584 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 4 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_13 = ./chan_fifo_readers_test.v
+Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181074819 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_14 = ../inband/usrp/fpga/inband_lib/usb_fifo_writer.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181183217 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
13 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_15 = ../inband/usrp/fpga/megacells/fifo_1k.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727110 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_16 = Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v
+Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726979 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
19 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_17 = ./usb_packet_fifo_test.v
+Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727437 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_18 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726990 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions 
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 5 
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_19 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181008809 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 7 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_20 = ./tx_buffer_test.v
+Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 3 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_21 = Z:/wc/simulations/channel_ram_test.v
+Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1181060194 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 
23 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_22 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
+Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180726982 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9 
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_23 = ./usb_fifo_reader_test.v
+Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top 
Level} last_compile 1180727438 cover_branch 0 vlog_noload 0 vlog_enable0In 0 
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 2 
dont_compile 0 cover_expr 0 cover_stmt 0
 Project_Sim_Count = 0
 Project_Folder_Count = 0
 Echo_Compile_Output = 0
@@ -321,6 +321,6 @@
 XML_CustomDoubleClick = 
 LOGFILE_DoubleClick = Edit
 LOGFILE_CustomDoubleClick = 
-EditorState = {tabbed horizontal 1} 
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 1} 
{Z:/wc/simulations/tx_buffer_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v 
0 0} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0} 
{Z:/wc/simulations/usb_fifo_writer_test.v 0 0}
+EditorState = {tabbed horizontal 1} 
{Z:/wc/inband/usrp/fpga/inband_lib/tx_buffer_inband.v 0 0} 
{Z:/wc/simulations/tx_buffer_test.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/tx_buffer.v 0 0} {Z:/wc/simulations/fake_fx2.v 
0 1} {Z:/wc/inband/usrp/fpga/inband_lib/chan_fifo_reader.v 0 0} 
{Z:/wc/inband/usrp/fpga/sdr_lib/strobe_gen.v 0 0} 
{Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v 0 0}
 Project_Major_Version = 6
 Project_Minor_Version = 1