[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r5738 - gnuradio/branches/developers/thottelt/inband/u
|
From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r5738 - gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib |
|
Date: |
Fri, 8 Jun 2007 13:15:38 -0600 (MDT) |
Author: thottelt
Date: 2007-06-08 13:15:37 -0600 (Fri, 08 Jun 2007)
New Revision: 5738
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
Log:
code cleaned up
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-08 16:57:49 UTC (rev 5737)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-06-08 19:15:37 UTC (rev 5738)
@@ -37,6 +37,12 @@
`define SEND 4'd6
`define DISCARD 4'd7
+ // Header format
+ `define PAYLOAD 8:0
+ `define ENDOFBURST 27
+ `define STARTDOFBURST 28
+
+
/* State registers */
reg [3:0] reader_state;
@@ -93,15 +99,15 @@
tx_empty <= 1 ;
//Check Start/End burst flag
- if (fifodata[28] == 1 && fifodata[27] == 1)
+ if (fifodata[`STARTDOFBURST] == 1
+ && fifodata[`ENDOFBURST] == 1)
burst <= 0;
- else if (fifodata[28] == 1)
+ else if (fifodata[`STARTDOFBURST] == 1)
burst <= 1;
- else if (fifodata[27] == 1)
+ else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
- payload_len <= fifodata[8:0] ;
- //payload_len <= 9'd504 ;
+ payload_len <= fifodata[`PAYLOAD] ;
read_len <= 0;
rdreq <= 0;
@@ -129,16 +135,12 @@
// Wait a little bit more
else if (timestamp > adc_time + `JITTER)
reader_state <= `WAIT;
-
-
// Outdated
else if (timestamp < adc_time)
begin
reader_state <= `DISCARD;
skip <= 1;
end
-
- //reader_state <= `WAITSTROBE;
end
// Wait for the transmit chain to be ready
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-08 16:57:49 UTC (rev 5737)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-06-08 19:15:37 UTC (rev 5738)
@@ -6,7 +6,7 @@
);
parameter NUM_CHAN = 2 ;
- /* Debug paramters */
+ /* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
@@ -28,8 +28,8 @@
output wire [15:0] tx_q_0 ;
output wire [15:0] tx_i_1 ;
output wire [15:0] tx_q_1 ;
+ output wire [15:0] debugbus ;
/* Not used yet */
- output wire [15:0] debugbus ;
output wire [15:0] tx_i_2 ;
output wire [15:0] tx_q_2 ;
output wire [15:0] tx_i_3 ;
@@ -80,26 +80,26 @@
/* Debug statement */
assign txstrobe_rate[0] = STROBE_RATE_0 ;
assign txstrobe_rate[1] = STROBE_RATE_1 ;
- assign tx_q_2 = 16'b0 ;
- assign tx_i_2 = 16'b0 ;
- assign tx_q_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
- assign debugbus = {7'b0, have_space, tx_empty, WR, chan_have_space[0],
- chan_have_space[1], bus_reset, reset, chan_txempty[0],
- chan_txempty[1]} ;
+ assign tx_q_2 = 16'b0 ;
+ assign tx_i_2 = 16'b0 ;
+ assign tx_q_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign debugbus = {7'b0, have_space, tx_empty, WR, chan_have_space[0],
+ chan_have_space[1], bus_reset, reset, chan_txempty[0],
+ chan_txempty[1]} ;
usb_fifo_writer tx_usb_packet_writer
(
- .bus_reset (bus_reset),
- .usbclk (usbclk),
- .WR_fx2 (WR),
- .usbdata (usbdata),
- .reset (reset),
- .txclk (txclk),
- .WR_channel (chan_WR),
- .WR_done_channel (chan_done),
- .ram_data (tx_data_bus)
+ .bus_reset (bus_reset),
+ .usbclk (usbclk),
+ .WR_fx2 (WR),
+ .usbdata (usbdata),
+ .reset (reset),
+ .txclk (txclk),
+ .WR_channel (chan_WR),
+ .WR_done_channel (chan_done),
+ .ram_data (tx_data_bus)
);
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-08 16:57:49 UTC (rev 5737)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-06-08 19:15:37 UTC (rev 5738)
@@ -36,9 +36,6 @@
WR_fx2_fixed <= WR_fx2 & ~write_count[8];
usbdata_fixed <= usbdata;
end
-
- /* make data 32 bits wide */
- //assign usbdata_packed = {usbdata_delayed, usbdata} ;
/* Used to convert 16 bits bus_data to the 32 bits wide fifo */
reg word_complete ;
@@ -67,7 +64,7 @@
end
else
writing <= 0 ;
- end
+ end
assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
assign WR_packed = word_complete & writing ;
@@ -88,7 +85,11 @@
reg WR_tx;
reg WR_1;
reg WR_2;
+ reg [31:0] usbdata_final;
+ reg WR_final;
+ always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
always @(posedge txclk)
if (reset)
WR_1 <= 0;
@@ -100,39 +101,6 @@
WR_2 <= 0;
else
WR_2 <= WR_1;
-
- always @(posedge txclk) usbdata_tx[0] <= usbdata_usbclk[0];
- always @(posedge txclk) usbdata_tx[1] <= #1 usbdata_usbclk[1];
- always @(posedge txclk) usbdata_tx[2] <= #2 usbdata_usbclk[2];
- always @(posedge txclk) usbdata_tx[3] <= #3 usbdata_usbclk[3];
- always @(posedge txclk) usbdata_tx[4] <= #4 usbdata_usbclk[4];
- always @(posedge txclk) usbdata_tx[5] <= #5 usbdata_usbclk[5];
- always @(posedge txclk) usbdata_tx[6] <= #6 usbdata_usbclk[6];
- always @(posedge txclk) usbdata_tx[7] <= #7 usbdata_usbclk[7];
- always @(posedge txclk) usbdata_tx[8] <= #8 usbdata_usbclk[8];
- always @(posedge txclk) usbdata_tx[9] <= #9 usbdata_usbclk[9];
- always @(posedge txclk) usbdata_tx[10] <= #10 usbdata_usbclk[10];
- always @(posedge txclk) usbdata_tx[11] <= #11 usbdata_usbclk[11];
- always @(posedge txclk) usbdata_tx[12] <= #12 usbdata_usbclk[12];
- always @(posedge txclk) usbdata_tx[13] <= #13 usbdata_usbclk[13];
- always @(posedge txclk) usbdata_tx[14] <= #14 usbdata_usbclk[14];
- always @(posedge txclk) usbdata_tx[15] <= #15 usbdata_usbclk[15];
- always @(posedge txclk) usbdata_tx[16] <= #16 usbdata_usbclk[16];
- always @(posedge txclk) usbdata_tx[17] <= #17 usbdata_usbclk[17];
- always @(posedge txclk) usbdata_tx[18] <= #18 usbdata_usbclk[18];
- always @(posedge txclk) usbdata_tx[19] <= #19 usbdata_usbclk[19];
- always @(posedge txclk) usbdata_tx[20] <= #20 usbdata_usbclk[20];
- always @(posedge txclk) usbdata_tx[21] <= #21 usbdata_usbclk[21];
- always @(posedge txclk) usbdata_tx[22] <= #22 usbdata_usbclk[22];
- always @(posedge txclk) usbdata_tx[23] <= #23 usbdata_usbclk[23];
- always @(posedge txclk) usbdata_tx[24] <= #1 usbdata_usbclk[24];
- always @(posedge txclk) usbdata_tx[25] <= #2 usbdata_usbclk[25];
- always @(posedge txclk) usbdata_tx[26] <= #3 usbdata_usbclk[26];
- always @(posedge txclk) usbdata_tx[27] <= #4 usbdata_usbclk[27];
- always @(posedge txclk) usbdata_tx[28] <= #5 usbdata_usbclk[28];
- always @(posedge txclk) usbdata_tx[29] <= #6 usbdata_usbclk[29];
- always @(posedge txclk) usbdata_tx[30] <= #7 usbdata_usbclk[30];
- always @(posedge txclk) usbdata_tx[31] <= #8 usbdata_usbclk[31];
always @(posedge txclk)
begin
@@ -142,9 +110,6 @@
WR_tx <= WR_1 & ~WR_2;
end
- reg [31:0] usbdata_final;
- reg WR_final;
-
always @(posedge txclk)
begin
if (reset)
@@ -157,22 +122,19 @@
end
end
-
-
-
/* Parse header and forward to ram */
reg [3:0]reader_state;
reg [4:0]channel ;
- reg [9:0]pkt_length ;
- reg [9:0]read_length ;
+ reg [9:0]read_length ;
parameter IDLE = 4'd0;
parameter HEADER = 4'd1;
- parameter FORWARD_HEADER = 4'd2;
- parameter WAIT = 4'd3;
- parameter FORWARD = 4'd4;
- parameter WAIT2 = 4'd5;
+ parameter WAIT = 4'd2;
+ parameter FORWARD = 4'd3;
+ `define CHANNEL 20:16
+ `define PKT_SIZE 512
+
always @(posedge txclk)
begin
if (reset)
@@ -181,58 +143,39 @@
WR_channel <= 0;
WR_done_channel <= 0;
end
- else
- case (reader_state)
- IDLE: begin
- if (WR_final)
- reader_state <= HEADER;
- end
+ else
+ case (reader_state)
+ IDLE: begin
+ if (WR_final)
+ reader_state <= HEADER;
+ end
- HEADER: begin
- channel <= (usbdata_final[20:16]) ;
- //channel <= 0 ;
- pkt_length <= usbdata_final[8:0] + 9'd8;
- read_length <= 10'd4 ;
-
- WR_channel[usbdata_final[20:16]] <= 1;
- //WR_channel[0] <= 1;
- ram_data <= usbdata_final;
- reader_state <= WAIT;
- end
+ // Store channel and forware header
+ HEADER: begin
+ channel <= (usbdata_final[`CHANNEL]) ;
+ WR_channel[usbdata_final[`CHANNEL]] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= 10'd4 ;
+
+ reader_state <= WAIT;
+ end
- FORWARD_HEADER: begin
- WR_channel[channel] <= 1;
- ram_data <= usbdata_final;
- reader_state <= WAIT;
- end
+ WAIT: begin
+ WR_channel[channel] <= 0;
+
+ if (read_length == `PKT_SIZE)
+ reader_state <= IDLE;
+ else if (WR_final)
+ reader_state <= FORWARD;
+ end
- WAIT: begin
- WR_channel[channel] <= 0;
-
- if (WR_final)
- begin
- reader_state <= FORWARD;
- end
- end
-
- FORWARD: begin
- WR_channel[channel] <= 1;
- ram_data <= usbdata_final;
- read_length <= read_length + 9'd4;
+ FORWARD: begin
+ WR_channel[channel] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= read_length + 10'd4;
- reader_state <= WAIT2;
- end
-
- WAIT2: begin
- WR_channel[channel] <= 0;
-
- if (read_length == 512)
- reader_state <= IDLE;
-
- if (WR_final)
- reader_state <= FORWARD;
- end
-
+ reader_state <= WAIT;
+ end
endcase
end
endmodule
\ No newline at end of file
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r5738 - gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib,
thottelt <=