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[Commit-gnuradio] r5740 - in gnuradio/branches/developers/jcorgan/sar/gr
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From: |
jcorgan |
|
Subject: |
[Commit-gnuradio] r5740 - in gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src: fpga/lib fpga/top python |
|
Date: |
Fri, 8 Jun 2007 13:40:48 -0600 (MDT) |
Author: jcorgan
Date: 2007-06-08 13:40:48 -0600 (Fri, 08 Jun 2007)
New Revision: 5740
Added:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
Removed:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/cordic_nco.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/Makefile.am
Log:
Work in progress.
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/cordic_nco.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/cordic_nco.v
2007-06-08 19:28:16 UTC (rev 5739)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/cordic_nco.v
2007-06-08 19:40:48 UTC (rev 5740)
@@ -19,13 +19,13 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-module
cordic_nco(clk_i,rst_i,ena_i,strobe_i,mag_i,freq_i,phs_i,data_i_o,data_q_o);
+module
cordic_nco(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,phs_i,data_i_o,data_q_o);
input clk_i;
input rst_i;
input ena_i;
input strobe_i;
- input [15:0] mag_i;
+ input [15:0] ampl_i;
input [31:0] freq_i;
input [31:0] phs_i;
@@ -34,7 +34,7 @@
reg [31:0] phase_reg;
wire [31:0] phase = phase_reg + phs_i;
- wire [15:0] mag;
+ wire [15:0] ampl;
always @(posedge clk_i)
begin
@@ -44,11 +44,11 @@
phase_reg <= phase_reg + freq_i;
end
- assign mag = ena_i ? mag_i : 16'b0;
+ assign ampl = ena_i ? ampl_i : 16'b0;
cordic tx_cordic
(.clock(clk_i),.reset(rst_in),.enable(strobe_i),
- .xi(mag),.yi(16'b0),.zi(phase[31:16]),
+ .xi(ampl),.yi(16'b0),.zi(phase[31:16]),
.xo(data_i_o),.yo(data_q_o),.zo());
endmodule // cordic_nco
Modified: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-06-08 19:28:16 UTC (rev 5739)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar.v
2007-06-08 19:40:48 UTC (rev 5740)
@@ -50,19 +50,18 @@
wire tx_enable; // Transmitter enable
wire rx_enable; // Receiver enable
- wire [13:0] mag; // temporary
+ wire [13:0] ampl;
wire [31:0] freq; // temporary
- wire [31:0] phs; // temporary
sar_control controller
(.clk_i(clk_i),.rst_i(1'b0),.ena_i(1'b1),
.s_strobe_i(s_strobe_i),.saddr_i(saddr_i),.sdata_i(sdata_i),
.reset_o(reset),.tx_ena_o(tx_enable),.rx_ena_o(rx_enable),
- .mag_o(mag),.freq_o(freq),.phs_o(phs));
+ .ampl_o(ampl),.freq_o(freq));
sar_tx transmitter
( .clk_i(clk_i),.rst_i(reset),.ena_i(tx_enable),
- .mag_i(mag),.freq_i(freq),.phs_i(phs),
+ .ampl_i(ampl),.freq_i(freq),
.strobe_i(tx_strobe_i),.tx_i_o(tx_dac_i_o),.tx_q_o(tx_dac_q_o) );
sar_rx receiver
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
2007-06-08 19:28:16 UTC (rev 5739)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_control.v
2007-06-08 19:40:48 UTC (rev 5740)
@@ -23,8 +23,7 @@
`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
module sar_control(clk_i,rst_i,ena_i,saddr_i,sdata_i,s_strobe_i,
- reset_o,tx_ena_o,rx_ena_o,
- mag_o,freq_o,phs_o);
+ reset_o,tx_ena_o,rx_ena_o,ampl_o,freq_o);
// System interface
input clk_i; // Master clock @ 64 MHz
@@ -39,9 +38,8 @@
output tx_ena_o;
output rx_ena_o;
- output [13:0] mag_o;
+ output [13:0] ampl_o;
output [31:0] freq_o;
- output [31:0] phs_o;
// Internal configuration
wire lp_ena;
@@ -53,8 +51,7 @@
setting_reg #(`FR_USER_0)
sr_mode(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),
.out({chirps,md_ena,dr_ena,lp_ena,rx_ena_o,tx_ena_o,reset_o}));
- setting_reg #(`FR_USER_1)
sr_mag(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(mag_o));
- setting_reg #(`FR_USER_2)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq_o));
- setting_reg #(`FR_USER_3)
sr_phs(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(phs_o));
+ setting_reg #(`FR_USER_5)
sr_ampl(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(ampl_o));
+ setting_reg #(`FR_USER_8)
sr_freq(.clock(clk_i),.reset(rst_i),.strobe(s_strobe_i),.addr(saddr_i),.in(sdata_i),.out(freq_o));
endmodule // sar_control
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-06-08 19:28:16 UTC (rev 5739)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/lib/sar_tx.v
2007-06-08 19:40:48 UTC (rev 5740)
@@ -19,10 +19,7 @@
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`include "../../../../usrp/firmware/include/fpga_regs_common.v"
-`include "../../../../usrp/firmware/include/fpga_regs_standard.v"
-
-module sar_tx(clk_i,rst_i,ena_i,strobe_i,mag_i,freq_i,phs_i,tx_i_o,tx_q_o);
+module sar_tx(clk_i,rst_i,ena_i,strobe_i,ampl_i,freq_i,tx_i_o,tx_q_o);
// System control
input clk_i;
input rst_i;
@@ -30,9 +27,8 @@
input strobe_i;
// Configuration
- input [13:0] mag_i;
+ input [13:0] ampl_i;
input [31:0] freq_i;
- input [31:0] phs_i;
// Output
output [13:0] tx_i_o;
@@ -41,7 +37,7 @@
wire [15:0] cordic_i, cordic_q;
cordic_nco
nco(.clk_i(clk_i),.rst_i(rst_i),.ena_i(ena_i),.strobe_i(strobe_i),
- .mag_i({2'b00,mag_i}),.freq_i(freq_i),.phs_i(phs_i),
+ .ampl_i({2'b00,ampl_i}),.freq_i(freq_i),.phs_i(0),
.data_i_o(cordic_i),.data_q_o(cordic_q));
assign tx_i_o = cordic_i[15:2];
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
===================================================================
---
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
2007-06-08 19:28:16 UTC (rev 5739)
+++
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/fpga/top/usrp_sar.srf
2007-06-08 19:40:48 UTC (rev 5740)
@@ -65,3 +65,5 @@
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\] data_in
GND " "Warning: Reduced register
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[1\]\" with
stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\] data_in
GND " "Warning: Reduced register
\"sar:sar\|sar_tx:transmitter\|cordic_nco:nco\|cordic:tx_cordic\|y0\[0\]\" with
stuck data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/cordic.v" "" { Text
"H:/gnuradio/sar/usrp/fpga/sdr_lib/cordic.v" 64 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG"
"master_control:master_control\|atr_delay:atr_delay\|state.0001 data_in GND "
"Warning: Reduced register
\"master_control:master_control\|atr_delay:atr_delay\|state.0001\" with stuck
data_in port to stuck value GND" { } { {
"../../../../usrp/fpga/sdr_lib/atr_delay.v" "" { Text
"H:/gnuradio/sar/usrp/fpga/sdr_lib/atr_delay.v" 31 -1 0 } } } 0 0 "Reduced
register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_ampl 14 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_ampl\" is connected to a
signal of width 14. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/sar_control.v" "sr_ampl" { Text
"H:/gnuradio/sar/gr-sar-fe/src/fpga/lib/sar_control.v" 54 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0}
+{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "out sr_mode 8 32 " "Warning:
Port \"out\" on the entity instantiation of \"sr_mode\" is connected to a
signal of width 8. The formal width of the signal in the module is 32. Extra
bits will be left dangling without any fanout logic." { } { {
"../lib/sar_control.v" "sr_mode" { Text
"H:/gnuradio/sar/gr-sar-fe/src/fpga/lib/sar_control.v" 52 0 0 } } } 0 0 "Port
\"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of
width %3!d!. The formal width of the signal in the module is %4!d!. Extra bits
will be left dangling without any fanout logic." 1 0}
Modified:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/Makefile.am
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/Makefile.am
2007-06-08 19:28:16 UTC (rev 5739)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/Makefile.am
2007-06-08 19:40:48 UTC (rev 5740)
@@ -21,7 +21,17 @@
include $(top_srcdir)/Makefile.common
+ourpythondir = $(grpythondir)
+ourlibdir = $(grpyexecdir)
+
EXTRA_DIST = \
- sar_tx.py
+ sar.py \
+ usrp_sar.py
+bin_SCRIPTS = \
+ usrp_sar.py
+
+ourpython_PYTHON = \
+ sar.py
+
MOSTLYCLEANFILES = *~ *.pyc *.pyo
Added: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
(rev 0)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar.py
2007-06-08 19:40:48 UTC (rev 5740)
@@ -0,0 +1,252 @@
+#!/usr/bin/env python
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr, usrp
+from gnuradio import eng_notation
+
+n2s = eng_notation.num_to_str
+
+#-----------------------------------------------------------------------
+# FPGA Register Definitions
+#-----------------------------------------------------------------------
+FR_SAR_MODE = usrp.FR_USER_0 # Operational mode
+bmFR_SAR_MODE_RESET = 1 << 0 # bit 0: active high reset
+bmFR_SAR_MODE_TX = 1 << 1 # bit 1: enable transmitter
+#bmFR_SAR_MODE_RX = 1 << 2 # bit 2: enable receiver
+#bmFR_SAR_MODE_LP = 1 << 3 # bit 3: enable digital loopback
+#bmFR_SAR_MODE_DR = 1 << 4 # bit 4: enable on-board deramping
+#bmFR_SAR_MODE_MD = 1 << 5 # bit 5: enable echo metadata
+#bmFR_SAR_MODE_CHIRPS = 3 << 6 # bit 6,7: number of chirp center frequencies
+
+#FR_SAR_TON = usrp.FR_USER_1 # 16-bit transmitter on time in clocks
+#FR_SAR_TSW = usrp.FR_USER_2 # 16-bit transmitter switch time in
clocks
+#FR_SAR_TLOOK = usrp.FR_USER_3 # 16-bit receiver look time in clocks
+#FR_SAR_TIDLE = usrp.FR_USER_4 # 32-bit inter-pulse idle time
+FR_SAR_AMPL = usrp.FR_USER_5 # 14-bit pulse amplitude (2s complement)
+#FR_SAR_FSTART = usrp.FR_USER_6 # 32-bit FTW for chirp start frequency
+#FR_SAR_FINCR = usrp.FR_USER_7 # 32-bit FTW increment per transmit clock
+
+# This is temporary for debugging transmitter frequency response
+FR_SAR_FREQ = usrp.FR_USER_8
+
+# These are for phase II development
+#FR_SAR_FREQ1N = usrp.FR_USER_8 # 24-bit N register for chirp #1
+#FR_SAR_FREQ1K = usrp.FR_USER_9 # 24-bit K register for chirp #1
+#FR_SAR_FREQ2N = usrp.FR_USER_10 # 24-bit N register for chirp #2
+#FR_SAR_FREQ2K = usrp.FR_USER_11 # 24-bit K register for chirp #2
+#FR_SAR_FREQ3N = usrp.FR_USER_12 # 24-bit N register for chirp #3
+#FR_SAR_FREQ3K = usrp.FR_USER_13 # 24-bit K register for chirp #3
+#FR_SAR_FREQ4N = usrp.FR_USER_14 # 24-bit N register for chirp #4
+#FR_SAR_FREQ4K = usrp.FR_USER_15 # 24-bit K register for chirp #4
+
+#-----------------------------------------------------------------------
+# Transmitter object. Uses usrp_sink, but only for a handle to the
+# FPGA registers.
+#-----------------------------------------------------------------------
+class sar_tx:
+ def __init__(self, verbose=False, debug=False):
+ self._verbose = verbose
+ self._debug = debug
+
+ self._u = usrp.sink_s(fpga_filename='usrp_sar.rbf')
+ self._subdev_spec = (0,0); # FPGA code only implements side A
+ self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
+ if self._verbose:
+ print "Using", self._subdev.name(), "for sar transmitter."
+
+ def tune(self, center_freq, waveform_freq):
+ self._center_freq = center_freq
+ self._waveform_freq = waveform_freq
+ self._ftw = int(waveform_freq*(2**32)/32e6)
+ if self._verbose:
+ print "Setting transmitter center frequency to", n2s(center_freq)
+ print "Setting waveform frequency offset to", n2s(waveform_freq),
"with ftw of", self._ftw
+ result = self._u.tune(0, self._subdev, center_freq)
+ if result == False:
+ raise RuntimeError("Failed to set transmitter frequency.")
+ self._u._write_fpga_reg(FR_SAR_FREQ, self._ftw)
+
+ def set_amplitude(self, ampl):
+ self._amplitude = ampl
+ if self._debug:
+ print "Writing amplitude register with:", hex(self._amplitude)
+ self._u._write_fpga_reg(FR_SAR_AMPL, self._amplitude)
+
+ def start(self):
+ self._u.start()
+
+
+#-----------------------------------------------------------------------
+# Receiver object. Uses usrp_source_c to receive echo records.
+# NOT IMPLEMENTED YET
+#-----------------------------------------------------------------------
+"""
+class sar_rx:
+ def
__init__(self,gain=None,msgq=None,loopback=False,verbose=False,debug=False):
+ self._gain = gain
+ self._msgq = msgq
+ self._loopback = loopback
+ self._verbose = verbose
+ self._debug = debug
+
+ self._fg = gr.flow_graph()
+ self._u = usrp.source_c(fpga_filename='usrp_sar.rbf')
+ if not self._loopback:
+ self._subdev_spec = (0,0) # FPGA only implements side A
+ self._u.set_mux(usrp.determine_rx_mux_value(self._u,
self._subdev_spec))
+ self._subdev = usrp.selected_subdev(self._u, self._subdev_spec)
+ if self._verbose:
+ print "Using", self._subdev.name(), "for sar receiver."
+
+ self.set_gain(self._gain)
+
+ # need to compute length here
+
+ self._vblen = gr.sizeof_gr_complex*self._length
+ if self._debug:
+ print "Generating echo vectors of length", self._length, "byte
length", self._vblen
+
+ self._s2v = gr.stream_to_vector(gr.sizeof_gr_complex, self._length)
+ self._sink = gr.message_sink(self._vblen, self._msgq, True)
+ self._fg.connect(self._u, self._s2v, self._sink)
+
+ def tune(self, frequency):
+ if self._verbose:
+ print "Setting receiver frequency to", n2s(frequency)
+ result = self._u.tune(0, self._subdev, frequency)
+ if result == False:
+ raise RuntimeError("Failed to set receiver frequency.")
+
+ def set_gain(self, gain):
+ self._gain = gain
+ if self._loopback:
+ return
+
+ if self._gain is None:
+ # if no gain was specified, use the mid-point in dB
+ g = self._subdev.gain_range()
+ self._gain = float(g[0]+g[1])/2
+ if self._verbose:
+ print "Setting receiver gain to", gain
+ self._subdev.set_gain(self._gain)
+
+ def start(self):
+ if self._debug:
+ print "Starting receiver flow graph."
+ self._fg.start()
+
+ def wait(self):
+ if self._debug:
+ print "Waiting for threads..."
+ self._fg.wait()
+
+ def stop(self):
+ if self._debug:
+ print "Stopping receiver flow graph."
+ self._fg.stop()
+ self.wait()
+ if self._debug:
+ print "Receiver flow graph stopped."
+"""
+
+class sar:
+ def __init__(self,msgq=None,verbose=False,debug=False):
+ self._msgq = msgq
+ self._verbose = verbose
+ self._debug = debug
+
+ self._mode = 0
+ self._transmitting = False
+ self._trans = sar_tx(verbose=self._verbose, debug=self._debug)
+ self.set_reset(True)
+
+ def set_amplitude(self, ampl):
+ self._trans.set_amplitude(ampl)
+
+ def tune(self, center_freq, waveform_freq):
+ self._trans.tune(center_freq, waveform_freq)
+
+ def _write_mode(self):
+ if self._debug:
+ print "Writing mode register with:", hex(self._mode)
+ self._trans._u._write_fpga_reg(FR_SAR_MODE, self._mode)
+
+ def enable_tx(self, value):
+ if value:
+ if self._verbose:
+ print "Enabling transmitter."
+ self._mode |= bmFR_SAR_MODE_TX
+ self._transmitting = True
+ else:
+ if self._verbose:
+ print "Disabling transmitter."
+ self._mode &= ~bmFR_SAR_MODE_TX
+ self._write_mode()
+
+ """
+ def enable_rx(self, value):
+ if value:
+ self._mode |= bmFR_SAR_MODE_RX
+ self._write_mode()
+ self._rcvr.start()
+ self._receiving = True
+ else:
+ self._rcvr.stop()
+ self._mode &= ~bmFR_SAR_MODE_RX
+ self._write_mode()
+ self._receiving = False
+ """
+ """
+ def set_loopback(self, value):
+ if value:
+ if self._verbose:
+ print "Enabling digital loopback."
+ self._mode |= bmFR_SAR_MODE_LP
+ else:
+ if self._verbose:
+ print "Disabling digital loopback."
+ self._mode &= ~bmFR_SAR_MODE_LP
+ self._write_mode()
+ """
+
+ def set_reset(self, value):
+ if value:
+ if self._debug:
+ print "Asserting reset."
+ self._mode |= bmFR_SAR_MODE_RESET
+ else:
+ if self._debug:
+ print "De-asserting reset."
+ self._mode &= ~bmFR_SAR_MODE_RESET
+ self._write_mode()
+
+ def start(self):
+ self.enable_tx(True)
+ self.set_reset(False)
+
+ def stop(self):
+ if self._transmitting:
+ self.enable_tx(False)
+ self.set_reset(True)
+
+ def __del__(self):
+ self.stop()
Deleted: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/sar_tx.py
Added: gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
(rev 0)
+++ gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
2007-06-08 19:40:48 UTC (rev 5740)
@@ -0,0 +1,94 @@
+#!/usr/bin/env python
+#
+# Copyright 2007 Free Software Foundation, Inc.
+#
+# This file is part of GNU Radio
+#
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING. If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+#
+
+from gnuradio import gr
+from gnuradio.sar import sar
+from gnuradio import eng_notation
+from gnuradio.eng_option import eng_option
+from optparse import OptionParser
+import sys
+
+n2s = eng_notation.num_to_str
+
+def main():
+ parser = OptionParser(option_class=eng_option)
+ #parser.add_option("-g", "--gain", type="eng_float", default=None,
+ # help="set gain in dB (default is midpoint)")
+ parser.add_option("-f", "--frequency", type="eng_float", default=0.0,
+ help="set transmitter center frequency to FREQ in Hz,
default is %default", metavar="FREQ")
+ # Temporary for debugging transmitter frequency response
+ parser.add_option("-w", "--waveform-frequency", type="eng_float",
default=0.0,
+ help="set waveform offset frequency to FREQ in Hz,
default is %default", metavar="FREQ")
+ parser.add_option("-a", "--amplitude", type="int", default=4096,
+ help="set waveform amplitude, default is %default,")
+ #parser.add_option("-l", "--loopback", action="store_true", default=False,
+ # help="enable digital loopback, default is disabled")
+ parser.add_option("-v", "--verbose", action="store_true", default=False,
+ help="enable verbose output, default is disabled")
+ parser.add_option("-D", "--debug", action="store_true", default=False,
+ help="enable debugging output, default is disabled")
+ #parser.add_option("-F", "--filename", default=None,
+ # help="log received impulse responses to file")
+
+ (options, args) = parser.parse_args()
+
+ if len(args) != 0:
+ parser.print_help()
+ sys.exit(1)
+
+ """
+ if options.filename == None:
+ print "Must supply filename for logging received data."
+ sys.exit(1)
+ else:
+ if options.verbose:
+ print "Logging impulse records to file: ", options.filename
+ """
+
+ msgq = gr.msg_queue()
+ s = sar(msgq=msgq,verbose=options.verbose,debug=options.debug)
+
+ s.set_amplitude(options.amplitude)
+ s.tune(options.frequency, options.waveform_frequency)
+ s.start()
+
+ """
+ f = open(options.filename, "wb")
+ print "Enter CTRL-C to stop."
+ try:
+ while (1):
+ msg = msgq.delete_head()
+ if msg.type() == 1:
+ break
+ rec = msg.to_string()
+ if options.debug:
+ print "Received echo vector of length", len(rec)
+ f.write(rec)
+
+ except KeyboardInterrupt:
+ pass
+ """
+
+ raw_input("Press enter to stop transmitting.")
+
+if __name__ == "__main__":
+ main()
Property changes on:
gnuradio/branches/developers/jcorgan/sar/gr-sar-fe/src/python/usrp_sar.py
___________________________________________________________________
Name: svn:executable
+ *
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